DSPIC33FJ16MC101-E/P Microchip Technology, DSPIC33FJ16MC101-E/P Datasheet - Page 46
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DSPIC33FJ16MC101-E/P
Manufacturer Part Number
DSPIC33FJ16MC101-E/P
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUB
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16MC101-E/P
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16MC101-E/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 46 of 322
- Download datasheet (5Mb)
TABLE 4-6:
TABLE 4-7:
TABLE 4-8:
TMR1
PR1
T1CON
TMR2
TMR3HLD 0108
TMR3
PR2
PR3
T2CON
T3CON
Legend:
IC1BUF
IC1CON
IC2BUF
IC2CON
IC3BUF
IC3CON
Legend:
OC1RS
OC1R
OC1CON
OC2RS
OC2R
OC2CON
Legend:
SFR Name
SFR Name
Name
SFR
Addr
0100
0102
0106
010A
010C
010E
SFR
0104
0110
0112
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
014A
SFR
0140
0142
0144
0146
0148
Addr
0180
0182
0184
0186
0188
018A
SFR
Bit 15
TON
TON
TON
TIMER REGISTER MAP
INPUT CAPTURE REGISTER MAP
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 15
—
—
—
—
—
Bit 14
—
—
—
Bit 14
Bit 14
—
—
—
—
—
Bit 13
TSIDL
TSIDL
TSIDL
OCSIDL
OCSIDL
ICSIDL
ICSIDL
ICSIDL
Bit 13
Bit 13
Bit 12
—
—
—
Bit 12
Bit 12
—
—
—
—
—
Bit 11
Bit 11
Bit 11
—
—
—
—
—
—
—
—
Bit 10
Bit 10
Bit 10
—
—
—
—
—
—
—
—
Timer3 Holding Register (for 32-bit timer operations only)
Bit 9
Bit 9
Bit 9
—
—
—
—
—
—
—
—
Output Compare 1 Secondary Register
Output Compare 2 Secondary Register
Output Compare 1 Register
Output Compare 2 Register
Input 1 Capture Register
Input 2 Capture Register
Input 3 Capture Register
Bit 8
Bit 8
Bit 8
—
—
Period Register 1
Period Register 2
Period Register 3
Timer1 Register
Timer2 Register
Timer3 Register
—
—
—
—
—
—
Bit 7
ICTMR
ICTMR
ICTMR
Bit 7
—
—
Bit 7
—
—
—
Bit 6
TGATE
TGATE
TGATE
—
—
Bit 6
Bit 6
ICI<1:0>
ICI<1:0>
ICI<1:0>
Bit 5
—
—
Bit 5
Bit 5
TCKPS<1:0>
TCKPS<1:0>
TCKPS<1:0>
OCFLT
OCFLT
Bit 4
ICOV
ICOV
ICOV
Bit 4
Bit 4
OCTSEL
OCTSEL
Bit 3
ICBNE
ICBNE
ICBNE
Bit 3
Bit 3
T32
—
—
Bit 2
Bit 2
TSYNC
Bit 2
—
—
OCM<2:0>
OCM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
Bit 1
Bit 1
Bit 1
TCS
TCS
TCS
Bit 0
Bit 0
Bit 0
—
—
—
Resets
Resets
xxxx
0000
xxxx
0000
xxxx
0000
Resets
xxxx
xxxx
0000
xxxx
xxxx
0000
All
0000
FFFF
0000
0000
xxxx
0000
FFFF
FFFF
0000
0000
All
All
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