DSPIC33FJ16MC102-I/ML Microchip Technology, DSPIC33FJ16MC102-I/ML Datasheet - Page 110
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DSPIC33FJ16MC102-I/ML
Manufacturer Part Number
DSPIC33FJ16MC102-I/ML
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16MC102-I/ML
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
21
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16MC102-I/ML
Manufacturer:
Microchip
Quantity:
288
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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 8-1:
DS70652C-page 110
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
CLKLOCK
R/W-0
U-0
—
2:
Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits (read-only)
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL)
010 = Primary Oscillator (MS, HS, EC)
011 = Primary Oscillator (MS, EC) with PLL
100 = Secondary Oscillator (S
101 = Low-Power RC Oscillator (LPRC)
110 = Fast RC Oscillator (FRC) with Divide-by-16
111 = Fast RC Oscillator (FRC) with Divide-by-n
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FCPLL)
010 = Primary Oscillator (MS, HS, EC)
011 = Primary Oscillator (MS, EC) with PLL
100 = Secondary Oscillator (S
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC Oscillator (FRC) with Divide-by-16
111 = Fast RC Oscillator (FRC) with Divide-by-n
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed
0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
Unimplemented: Read as ‘0’
IOLOCK
R/W-0
R-0
OSCCON: OSCILLATOR CONTROL REGISTER
COSC<2:0>
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
LOCK
R-0
R-0
OSC
OSC
R-0
U-0
Preliminary
—
)
)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0
U-0
CF
—
R/W-y
(1)
U-0
—
© 2011 Microchip Technology Inc.
NOSC<2:0>
x = Bit is unknown
LPOSCEN
R/W-0
R/W-y
(2)
OSWEN
R/W-y
R/W-0
bit 8
bit 0
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