DSPIC33FJ16MC102T-I/ML Microchip Technology, DSPIC33FJ16MC102T-I/ML Datasheet - Page 178

• Manufacturer Part Number: DSPIC33FJ16MC102T-I/ML
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 QFN 6x6mm T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC102T-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 17-1:
DS70652C-page 178
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0 = Start condition not in progress
Hardware clear at end of master Acknowledge sequence
master Repeated Start sequence
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C master, applicable during master receive)
2
C. Hardware clear at end of eighth bit of master receive data byte
Preliminary
2
C master)
2
2
2
C master, applicable during master receive)
C master)
C master)
2
C master)
© 2011 Microchip Technology Inc.