DSPIC33FJ16MC304-H/ML Microchip Technology, DSPIC33FJ16MC304-H/ML Datasheet - Page 2

• Manufacturer Part Number: DSPIC33FJ16MC304-H/ML
• Description: 16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. I
13. I
14. Product Identification
15. UART (UxE Interrupt)
16. UART Module
17. Internal Voltage Regulator
18. PSV Operations
DS80338D-page 2
The ACKSTAT bit is cleared shortly after being set
following a slave transmit.
When the I
addressing using the same address bits (A10 and
A9) as other I
work as expected.
Revision A2 devices marked as extended temper-
ature range (E) devices, support only industrial
temperature range (I).
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
When the UART module is operating in 8-bit mode
(PDSEL
encoder/decoder
incorrectly transmits a data payload of 80h as 00h.
When the VREGS (RCON<8>) bit is set to a logic
‘0’ higher sleep current may be observed.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
2
2
C Module
C Module: 10-bit Addressing Mode
=
2
C module is configured for 10-bit
2
C device A10 and A9 bits may not
0x)
(IREN
and
=
using
1),
the
the
module
IrDA
®
19. I
20. I
21. I
22. Motor Control PWM – Operation in DOZE Mode
23. Quadrature Encoder Interface
The following sections describe the errata and work
around to these errata, where they may apply.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
With the I
external
associated with SCL and SDA pins will not reflect
the actual digital logic levels on the pins.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
The Motor Control PWM module generates more
interrupts than expected when DOZE mode is
used and the output postscaler value is different
than 1:1.
The Quadrature Encoder Interface module does
not generate an interrupt in a particular overflow
condition.
2
2
2
C Module: 10-bit Addressing Mode
C Module
C Module: 10-bit Addressing Mode
2
Interrupt
C module enabled, the PORT bits and
2
C module is configured as a 10-bit
© 2008 Microchip Technology Inc.
Input
functions
(if
any)