DSPIC33FJ256MC510A-E/PF Microchip Technology, DSPIC33FJ256MC510A-E/PF Datasheet - Page 3

• Manufacturer Part Number: DSPIC33FJ256MC510A-E/PF
• Description: 16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510A-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: ECAN
© 2010 Microchip Technology Inc.
Note:
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake functions continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
A3
X
repetitive
Interrupt
dsPIC33FJ256MCX06A/X08A/X10A
Service
Routine
2. Module: ECAN
3. Module: QEI
In
transmissions and receptions using ECAN with
DMA, intermittent DMA Write Collisions might get
generated, resulting in the generation of DMA
Error Traps. The ECAN messages would be
transmitted and received correctly even when
these DMA Error Traps occur.
Work around
Within the DMA Error Trap service routine in the
application software, read the DMACS0 register
and inspect the two XWCOLn (n = 0, 1, …,7) bits
corresponding to the DMA channels being used for
ECAN transmission and reception.
For example, if DMA Channel 1 is used for ECAN
Reception and DMA Channel 2 is used for ECAN
Transmission, inspect the XWCOL1 and XWCOL2
bits. If either of these bits is found to be set, clear
the DMACERR bit in the INTCON1 register and
return from the DMA Error Trap service routine.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
A2
A2
X
X
user
A3
A3
X
applications
that
DS80484D-page 3
perform
both