DSPIC33FJ256MC510A-E/PF Microchip Technology, DSPIC33FJ256MC510A-E/PF Datasheet - Page 196
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DSPIC33FJ256MC510A-E/PF
Manufacturer Part Number
DSPIC33FJ256MC510A-E/PF
Description
16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ256MC510A-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256MC510A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 196 of 352
- Download datasheet (3Mb)
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 17-2:
DS70594B-page 196
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-9
bit 8
bit 7
bit 6-4
bit 3-0
QEOUT
R/W-0
U-0
—
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits
These bits allow the user to specify the state of the QEAx and QEBx input pins during an index pulse
when the POSxCNT register is to be reset.
In 4X Quadrature Count Mode:
IMV1 = Required state of Phase B input signal for match on index pulse
IMV0 = Required state of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1 = Selects phase input signal for index state match (0 = Phase A, 1 = Phase B)
IMV0 = Required state of the selected Phase input signal for match on index pulse
CEID: Count Error Interrupt Disable bit
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits
111 = 1:256 clock divide
110 = 1:128 clock divide
101 = 1:64 clock divide
100 = 1:32 clock divide
011 = 1:16 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
Unimplemented: Read as ‘0’
U-0
—
DFLTxCON: DIGITAL FILTER x CONTROL REGISTER
W = Writable bit
QECK<2:0>
‘1’ = Bit is set
R/W-0
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
R/W-0
U-0
—
IMV<2:0>
2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
R/W-0
CEID
U-0
—
bit 8
bit 0
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