DSPIC33FJ32GP204-H/ML Microchip Technology, DSPIC33FJ32GP204-H/ML Datasheet - Page 112

16-bit DSC, 44LD,32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE

DSPIC33FJ32GP204-H/ML

Manufacturer Part Number
DSPIC33FJ32GP204-H/ML
Description
16-bit DSC, 44LD,32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ32GP204-H/ML

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-VQFN Exposed Pad
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 9-2:
DS70290G-page 112
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9
bit 8
bit 7-2
bit 1
bit 0
IC8MD
R/W-0
U-0
IC8MD: Input Capture 8 Module Disable bit
1 = Input Capture 8 module is disabled
0 = Input Capture 8 module is enabled
IC7MD: Input Capture 2 Module Disable bit
1 = Input Capture 7 module is disabled
0 = Input Capture 7 module is enabled
Unimplemented: Read as ‘0’
IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
Unimplemented: Read as ‘0’
OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
IC7MD
R/W-0
U-0
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
U-0
U-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
OC2MD
IC2MD
R/W-0
R/W-0
OC1MD
IC1MD
R/W-0
R/W-0
bit 8
bit 0

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