DSPIC33FJ64GP310A-I/PF Microchip Technology, DSPIC33FJ64GP310A-I/PF Datasheet - Page 2
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DSPIC33FJ64GP310A-I/PF
Manufacturer Part Number
DSPIC33FJ64GP310A-I/PF
Description
16 Bit MCU/DSP 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64GP310A-I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64GP310A-I/PF
Manufacturer:
MAXIM
Quantity:
275
Company:
Part Number:
DSPIC33FJ64GP310A-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 1:
TABLE 2:
DS80465D-page 2
dsPIC33FJ128GP706A
dsPIC33FJ128GP708A
dsPIC33FJ128GP710A
Note 1:
Note 1:
Operations
Regulator
Module
Internal
Voltage
ECAN
UART
UART
UART
I
CPU
PSV
2
SPI
SPI
I
I
I
C™
2
2
2
C
C
C
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
Frame Mode
Sleep Mode
High-Speed
Addressing
Addressing
Addressing
Instruction
Operation
Interrupts
IR Mode
Transmit
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
Feature
Mode
10-bit
Mode
10-bit
Mode
10-bit
Mode
EXCH
I
—
—
PD
Number
Item
10.
12.
13.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using two Stop
bits (STSEL = 1), it may sample the first Stop bit instead of the
second one.
The UART error interrupt may not occur, or may occur at an
incorrect time, if multiple errors occur during a short period of
time.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
After the ACKSTAT bit is set when receiving a NACK, it may be
cleared by the reception of a Start or Stop bit.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant bits
(LSbs) of the address are the same as the 7-bit reserved
addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
In framed SPI mode, when the FRMDLY bit (SPIxCON2<1>) is
cleared and SMP bit (SPIxCON1<9>) is cleared, frame sync
pulses do not get generated.
When the VREGS bit (RCON<8>) is set to a logic ‘0’, device
may Reset and higher sleep current may be observed.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The EXCH instruction does not execute correctly.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause SPI module to ignore written data.
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
Device ID
0x00ED
0x00EE
0x00EF
(1)
Issue Summary
Revision ID for Silicon Revision
0x3009
2
A3
C devices, the
© 2010 Microchip Technology Inc.
0x300A
Revisions
A3
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
(2)
(1)