DSPIC33FJ64GP804-E/ML Microchip Technology, DSPIC33FJ64GP804-E/ML Datasheet - Page 34
![16-bit DSC, 64KB Flash,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ64GP804-E/ML
Manufacturer Part Number
DSPIC33FJ64GP804-E/ML
Description
16-bit DSC, 64KB Flash,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64GP804-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Overflow and Saturation Status bits can
optionally be viewed in the STATUS Register (SR)
as the logical OR of OA and OB (in bit OAB) and the
logical OR of SA and SB (in bit SAB). Programmers
can check one bit in the STATUS register to
determine if either accumulator has overflowed, or
one bit to determine if either accumulator has
saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
• Bit 31 Overflow and Saturation:
• Bit 39 Catastrophic Overflow:
3.7.3
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
• [W13] + = 2, Register Indirect with Post-Increment:
DS70292E-page 34
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31 value
(0x8000000000) into the target accumulator. The
SA or SB bit is set and remains set until cleared by
the user application. This condition is referred to as
‘super saturation’ and provides protection against
erroneous data or unexpected algorithm problems
(such as gain calculations).
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
ACCUMULATOR ‘WRITE BACK’
3.7.3.1
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accu-
mulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accu-
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
A consequence of this algorithm is that over a succes-
sion of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (bit 16 of the accumulator) of ACCxH is
examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the
Section 3.7.3.2 “Data Space Write
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
mulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
is left unchanged.
X
bus,
Round Logic
subject
© 2011 Microchip Technology Inc.
to
data
Saturation”). For
saturation
(see
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