DSPIC33FJ64MC710AT-I/PF Microchip Technology, DSPIC33FJ64MC710AT-I/PF Datasheet - Page 239
![16 Bit MCU/DSP 40MIPS 64KB FLASH 100 TQFP 14x14x1mm T/R](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64MC710AT-I/PF
Manufacturer Part Number
DSPIC33FJ64MC710AT-I/PF
Description
16 Bit MCU/DSP 40MIPS 64KB FLASH 100 TQFP 14x14x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64MC506A-IPT.pdf
(352 pages)
Specifications of DSPIC33FJ64MC710AT-I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC710AT-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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REGISTER 21-26:
2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
TXENm
TXENn
R/W-0
R/W-0
This bit is cleared when TXREQ is set.
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
TXABTm: Message Aborted bit
1 = Message was aborted
0 = Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message
is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
TXABTm
TXABTn
R-0
R-0
CiTRmnCON: ECAN TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7)
dsPIC33FJXXXMCX06A/X08A/X10A
(1)
W = Writable bit
‘1’ = Bit is set
TXLARBm
TXLARBn
R-0
R-0
(1)
TXERRm
TXERRn
(1)
R-0
R-0
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQm
TXREQn
R/W-0
R/W-0
(1)
RTRENm
RTRENn
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
TXmPRI<1:0>
TXnPRI<1:0>
DS70594B-page 239
R/W-0
R/W-0
bit 8
bit 0
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