EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 172

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

9–12
Table 9–7. Cyclone III Device Family Configuration Schemes
AS Configuration (Serial Configuration Devices)
Cyclone III Device Handbook, Volume 1
Fast Passive Parallel Fast (FPP Fast POR)
with Encryption (for Cyclone III LS
devices only)
JTAG-based configuration
Notes to
(1) Altera recommends connecting the MSEL pins to V
(2) The configuration voltage standard is applied to the V
(3) You must follow specific requirements when interfacing Cyclone III device family with 2.5-, 3.0-, and 3.3-V configuration voltage standards. For
(4) FPP configuration is not supported in the Cyclone III E144 device package of Cyclone III devices.
(5) The JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored.
(6) Do not leave the MSEL pins floating. Connect them to V
more information about these requirements, refer to
Altera recommends connecting the MSEL pins to GND if your device is only using the JTAG configuration.
Table
Configuration Scheme
f
9–7:
In the AS configuration scheme, Cyclone III device family is configured using a serial
configuration device. These configuration devices are low-cost devices with
non-volatile memories that feature a simple four-pin interface and a small form factor.
These features make serial configuration devices the ideal low-cost configuration
solution.
For more information about serial configuration devices, refer to the
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
In Cyclone III device family, the active master clock frequency runs at a maximum of
40 MHz, and typically at 30 MHz. Cyclone III device family only work with serial
configuration devices that support up to 40 MHz.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Cyclone III device family reads configuration data using
the serial interface, decompress data if necessary, and configure their SRAM cells. This
scheme is referred to as the AS configuration scheme because the device controls the
configuration interface.
Single-Device AS Configuration
The four-pin interface of serial configuration devices consists of the following pins:
■
■
■
■
This four-pin interface connects to Cyclone III device family pins, as shown in
Figure
(5)
Serial clock input (DCLK)
Serial data output (DATA)
AS data input (ASDI)
Active-low chip select (nCS)
9–3.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
CCA
“Configuration and JTAG Pin I/O Requirements” on page
CCIO
(6)
CCA
or GND depending on the MSEL pin settings.
3
0
supply of the bank in which the configuration pins reside.
or GND. These pins support the non-JTAG configuration scheme used in production.
(6)
2
1
MSEL
(Note 1)
(6)
1
1
(Part 2 of 2)
(6)
0
0
Configuration Voltage Standard (V)
© December 2009 Altera Corporation
9–7.
(2),(3)
1.8/1.5
—
Serial
Configuration Features