EPF10K200SFC484-1N Altera, EPF10K200SFC484-1N Datasheet - Page 61

• Manufacturer Part Number: EPF10K200SFC484-1N
• Description: FLEX 10KE
• Manufacturer: Altera

Specifications of EPF10K200SFC484-1N

• Family Name: FLEX 10KE
• Number Of Usable Gates: 200000
• Number Of Logic Blocks/elements: 9984
• # Registers: 369
• # I/os (max): 369
• Frequency (max): 250MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 9984
• Ram Bits: 98304
• Device System Gates: 513000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
INH
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 30. External Bidirectional Timing Parameters
Symbol
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
Operating conditions: VCCIO = 3.3 V ±10% for commercial or industrial use.
Operating conditions: VCCIO = 2.5 V ±5% for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF10K100E, EPF10K130E, and EPF10K200S devices.
Operating conditions: VCCIO = 3.3 V.
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Contact Altera Applications for test circuit specifications and test conditions.
This timing parameter is sample-tested only.
Bus Specification, revision 2.2.
Setup time for bi-directional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Hold time with global clock at IOE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate= off
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Parameter
Note (9)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
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