EPF6016AQC208-1N Altera, EPF6016AQC208-1N Datasheet - Page 25

• Manufacturer Part Number: EPF6016AQC208-1N
• Description: FLEX 6000
• Manufacturer: Altera

Specifications of EPF6016AQC208-1N

• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # I/os (max): 171
• Frequency (max): 200MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Figure 14. IOE Connection to Column Interconnect
SameFrame
Pin-Outs
Altera Corporation
Any LE can drive a
pin through the row
and local interconnect.
FastFLEX I/O: An
LE can drive a
pin through a local
interconnect for faster
clock-to-output times.
3.3-V FLEX 6000 devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support an EPF6016A device in a 100-pin FineLine BGA package or an
EPF6024A device in a 256-pin FineLine BGA package.
The Altera software packages provide support to design PCBs with
SameFrame pin-out devices. Devices can be defined for present and future
use. The Altera software packages generate pin-outs describing how to lay
out a board to take advantage of this migration (see
Row Interconnect
IOE
Each IOE can drive two
column interconnect channels.
Each IOE data and OE signal is
driven to a local interconnect.
FLEX 6000 Programmable Logic Device Family Data Sheet
LAB
IOE
Column Interconnect
Figure
15).
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