EPM7512AEQC208-12N Altera, EPM7512AEQC208-12N Datasheet - Page 32
EPM7512AEQC208-12N
Manufacturer Part Number
EPM7512AEQC208-12N
Description
MAX 7000/S/AE/B
Manufacturer
Altera
Datasheet
1.EPM7128AELC84-10N.pdf
(64 pages)
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MAX 7000A Programmable Logic Device Data Sheet
Figure 11. MAX 7000A Timing Model
32
Delay
f
Input
t
I N
Delay
PIA
t
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
See
information.
Application Note 94 (Understanding MAX 7000 Timing)
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
Delay
t
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
Expander Delay
Parallel
t
PEXP
Figure 12
Input Delay
Fast
t
F I N
Register
t
t
t
t
t
t
t
t
shows the timing relationship
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
Altera Corporation
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
for more
Delay
I/O
t
I O
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