EPM7512AETC144-7N Altera, EPM7512AETC144-7N Datasheet - Page 2
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EPM7512AETC144-7N
Manufacturer Part Number
EPM7512AETC144-7N
Description
MAX 7000/S/AE/B
Manufacturer
Altera
Datasheet
1.EPM7512AETC144-7N.pdf
(64 pages)
Specifications of EPM7512AETC144-7N
Family Name
MAX 7000A
Memory Type
EEPROM
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
32
# I/os (max)
120
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
2
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
t
t
t
f
PD
SU
FSU
CO1
CNT
Table 1. MAX 7000A Device Features
(ns)
(ns)
(ns)
(ns)
(MHz)
Feature
EPM7032AE
227.3
600
4.5
2.9
2.5
3.0
32
36
2
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
packages
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
PCI-compatible
Bus-friendly architecture, including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
Programmable output slew-rate control
Programmable ground pins
EPM7064AE
1,250
222.2
4.5
2.8
2.5
3.1
64
68
TM
4
I/O interface enables device core to run at 3.3 V, while
TM
EPM7128AE
, and plastic J-lead chip carrier (PLCC)
2,500
192.3
128
100
5.0
3.3
2.5
3.4
8
EPM7256AE
5,000
172.4
256
164
5.5
3.9
2.5
3.5
16
Altera Corporation
EPM7512AE
10,000
116.3
512
212
7.5
5.6
3.0
4.7
32