EVAL-AD7291SDZ Analog Devices Inc, EVAL-AD7291SDZ Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD7291SDZ
• Description: Evaluation Control Board
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD7291SDZ

• Rohs Compliant: YES
• Silicon Manufacturer: Analog Devices
• Kit Application Type: Interface
• Application Sub Type: ADC
• Features: Channel Sequencer Operation, Alert Function, Autocycle Mode
• Number Of Adc's: 8
• Number Of Bits: 12
• Sampling Rate (per Second): 22.22k
• Data Interface: I²C
• Input Range: -
• Power (typ) @ Conditions: -
• Operating Temperature: -
• Utilized Ic / Part: AD7291
• Silicon Core Number: AD7291
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The example in Figure 28 shows the command mode convert-
ing on a sequence of channels including V
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The master sends the result register address (0x01).
11. The slave asserts an acknowledge on SDA.
12. The master sends the 7-bit slave address followed by the
13. The slave (AD7291) asserts an acknowledge on SDA.
14. The master receives a data byte, which contains the
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device (AD7291) asserts an
acknowledge on SDA.
The master sends the command register address (0x00).
The slave asserts an acknowledge on SDA.
The master sends the first data byte (0xE0) to the command
register, which selects the V
The slave asserts an acknowledge on SDA.
The master sends the second data byte (0x20) to the com-
mand register.
The slave asserts an acknowledge on SDA.
write bit (high).
channel address bits and the four MSBs of the converted
result for Channel V
*
S
...
...
...
...
= POSITION OF SAMPLING START
*
CH AD (0010)
SLAVE ADDRESS
POINT TO RESULT REG (0x01)
V
V
IN0
IN0
[7:0]
[7:0]
IN0
.
A
A
V
*
IN2
0
IN0
CH AD (0001)
........
[11:8]
, V
SA
IN1
, and V
IN0
POINT TO COMMAND REG (0x00)
SA
A
, V
V
IN2
IN2
V
IN1
SR
[7:0]
IN1
, and V
channels.
[11:8]
V
IN2
SLAVE ADDRESS
Figure 28. Command Mode Operation
[7:0]
IN2
A
.
A
Rev. 0 | Page 25 of 28
P
A
V
*
IN1
CH ID (0000)
[7:0]
1
SA
15. The master then asserts an acknowledge on SDA.
16. The master receives the second data byte, which contains
17. Step 11 and Step 12 repeat for Channel V
18. Once the master has received the results from all the
19. The master asserts a not acknowledge on SDA and a stop
To change the conversion sequence, rewrite a new sequence to
the command mode. If a new write to the command register is
performed while an existing conversion sequence is underway,
the existing conversion sequence is terminated and the next
conversion performed is the first selected channel from the new
sequence. The maximum throughput that can be achieved using
this mode with a 400 kHz I
SA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
*
A
CH AD (0000)
the eight LSBs of the converted result for Channel V
master then asserts on acknowledge on SDA.
Channel V
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Step 12 to Step 14 are repeated.
condition on SDA to end the conversion and exit
command mode.
COMMAND = 0xE0
...
V
IN0
[11:8]
IN2
.
V
IN0
A
[11:8]
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
...
SA
2
C clock is (400 kHz/18) = 22.2 kSPS.
COMMAND = 0x20
A
...
IN1
and
SA
AD7291
IN0
. The