KSZ8841-32MVLI Micrel Inc, KSZ8841-32MVLI Datasheet - Page 53

Single Ethernet Port + Generic (32-bit) Bus Interface( )

KSZ8841-32MVLI

Manufacturer Part Number
KSZ8841-32MVLI
Description
Single Ethernet Port + Generic (32-bit) Bus Interface( )
Manufacturer
Micrel Inc
Datasheets

Specifications of KSZ8841-32MVLI

Controller Type
Ethernet Controller, MAC
Interface
Bus
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-LQFP
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Industrial
Package Type
LQFP
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1632 - BOARD EVALUATION KSZ8841-16MVL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-2983

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8841-32MVLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR
This register contains the user defined QMU RX Queue high watermark configuration bit as below.
Bank 0 Bus Error Status Register (0x06): BESR
This register flags the different kinds of errors on the host bus.
Bank 0 Bus Burst Length Register (0x08): BBLR
Before the burst can be sent, the burst length needs to be programmed.
Bank 1: Reserved
Except Bank Select Register (0xE).
October 2007
Micrel, Inc.
Bit
15-13
12
11-0
Bit
15
14-11
10
9-0
Bit
15
14-12
11-0
0x0
0
0
-
0
0
Default Value
0x000
Default Value
0x000
Default Value
0x0
0x000
R/W
RO
RW
RO
R/W
RO
RO
RO
RO
R/W
RO
RW
RO
Description
Reserved
QMU RX Flow Control High Watermark Configuration
0: 3 KBytes
1: 2 KBytes
Reserved
Description
IBEC Illegal Byte Enable Combination
1: illegal byte enable combination occurs. The illegal combination value can be found
from bit 14 to bit 11.
0: legal byte enable combination.
Write 1 to clear.
IBECV Illegal Byte Enable Combination Value
Bit 14: byte enable 3.
Bit 13: byte enable 2.
Bit 12: byte enable 1.
Bit 11: byte enable 0.
This value is valid only when bit 15 is set to 1.
SSAXFER Simultaneous Synchronous and Asnychronous Transfers
1: Synchronous and Asnychronous Transfers occur simultaneously.
0: normal.
Write 1 to clear.
Reserved.
Description
Reserved.
BRL Burst Length (for burst read and write)
000: single.
011: fixed burst read length of 4.
101: fixed burst read length of 8.
111: fixed burst read length of 16.
Reserved.
53
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6

Related parts for KSZ8841-32MVLI