IR5001S International Rectifier, IR5001S Datasheet - Page 10

• Manufacturer Part Number: IR5001S
• Description: IC CTRLR/MOSFET UNIV N-CH 8SOIC
• Manufacturer: International Rectifier

Specifications of IR5001S

• Applications: -48V Dist Power Systems, AdvancedTCA ® Systems
• Fet Type: N-Channel
• Number Of Outputs: 1
• Internal Switch(s): No
• Delay Time - On: 27µs
• Delay Time - Off: 130ns
• Voltage - Supply: 36 V ~ 75 V
• Current - Supply: 500µA
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Package: 8-lead SOIC Narrow
• Input Voltage: 100V Max Continuous
• Vline: 36V to 75V 100V Max or 12Vreg
• Offset Voltage (v): -7.9mV min to 0V max
• Turn-on Time (ns): 20
• Turn-off Time (ns): 130
• T Off Gate Drive: 3A Peak
• Junction Temperature: -40oC to 125oC
• Special Ic: FetCheck Available
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *IR5001S

IR5001
APPLICATION INFORMATION
The IR5001 is designed for multiple active ORing
and reverse polarity protection applications with
minimal number of external components. Examples
of typical circuit connections are shown below.
Negative Rail ORing/Reverse Polarity Protection
rail Active ORing or reverse polarity protection is
shown in Fig. 17. In this example, IR5001 is biased
directly from the positive rail. However, any of the
biasing schemes shown in Fig. 16 can be used.
boards, one IR5001 is used per feed. This is shown
in Fig.1. An evaluation kit is available for typical
system boards, with input voltages of negative 36V
to negative 75V, and for power levels from 30W to
about 300W. The p/n for the evaluation kit is
IRDC5001-LS48V.
detailed
performance data for the IR5001.
Figure. 17 Connection of INN, INP, and Gnd for negative
rail Active ORing or reverse polarity protection.
Figure. 18. Connection of INN,INP, and Gnd when the
MOSFET is placed in the path of positive rail.
10
Vin -
Vin +
Vbias
Vout +
Vout -
Vbias
A typical connection of the IR5001 in negative
For input ORing in carrier-class communications
+
+
Rbias
Rbias
design
Vline
Vcc
FETch
FETst
Vline
Vcc
FETst
FETch
considerations
IR5001
IR5001
This evaluation kit contains
OUT
Gnd
INN
OUT
INP
Gnd
INN
INP
and
Redundant Vout +
Redundant Vin -
in-circuit
Load
www.irf.com
Load
Positive Rail ORing / Ground ORing in
Communications Boards
rail ORing is shown in Fig. 18. Typical applications
are inside redundant AC-DC and DC-DC power
supplies, or on-board ORing. For positive rail ORing,
an additional Vbias voltage above the positive rail is
needed to bias the IR5001.
rail ORing is available under p/n IRAC5001-
HS100A, demonstrating performance of the IR5001
at 100A output current.
Considerations for the Selection of the Active
ORing N-Channel MOSFET
losses, and depend on the source-drain current and
R
virtually eliminated if a FET with very low R
was used. However, using arbitrarily low R
not desirable for three reasons:
1. Turn off propagation delay. Higher R
2. Undetected reverse (drain to source) current
3. Cost. With properly selected R
DS(on)
An example of a typical connection in positive
An evaluation kit for high-current 12V positive
Active ORing FET losses are all conduction
provide more voltage information to the internal
comparator faster, and will result in faster FET
turn off protection in case of short-circuit of the
source
redundant bus.
flow. With the asymmetrical offset voltage, some
small current can flow from the drain to source
of the ORing FET and be undetected by the
IR5001. The amount of undetected drain-source
current depends on the R
MOSFET and its R
(drain-source) current below 5 – 10% of the
nominal source-drain state, the R
selected FET should produce 50mV to 100mV of
the voltage drop during nominal operation.
ORing
competitive
providing huge power loss reduction. For
example, a FET with 20mOhm R
60mV voltage drop at 3A; associated power
savings compared to the traditional diode ORing
(assuming typical 0.6V forward voltage drop) is
ten fold(0.18W vs. 1.8W)!
FET R
would be reduced by additional 90mW, which is
negligible compared to the power loss reduction
already achieved with 20mOhm FET. But to get
this negligible saving, the cost of the Active
ORing FET would increase significantly.
of the FET. The conduction loss could be
DS(on)
using
(less
with
was 10mOhm. The power loss
voltage
IR5001
DS(on)
traditional
. To keep the reverse
disturbance
can
DS(on)
Now assume that
be
DS(on)
of the selected
ORing
DS(on)
DS(on)
very
DS(on)
results in
, Active
DS(on)
on
of the
DS(on)
while
cost
will
the
is