AD9861BCP-80 Analog Devices Inc, AD9861BCP-80 Datasheet
AD9861BCP-80
Specifications of AD9861BCP-80
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AD9861BCP-80 Summary of contents
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FEATURES Receive path includes dual 10-bit analog-to-digital converters with internal or external reference, 50 MSPS and 80 MSPS versions Transmit path includes dual 10-bit, 200 MSPS digital-to- analog converters with 1×, 2×, or 4× interpolation and programmable gain control Internal ...
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AD9861 TABLE OF CONTENTS Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Pin Function Descriptions...................... 8 Typical Performance Characteristics ........................................... 10 ...
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Tx PATH SPECIFICATIONS Table 1. AD9861-50 and AD9861- 200 MSPS; 4× interpolation; R DAC SET unless otherwise noted Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch ...
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AD9861 Rx PATH SPECIFICATIONS Table 2. AD9861-50 and AD9861- MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC ADC_AVDD = DVDD = 3.3V, unless otherwise noted Parameter Rx PATH GENERAL Resolution ...
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POWER SPECIFICATIONS Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3 Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) TxPath ...
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AD9861 TIMING SPECIFICATIONS Table 5. AD9861-50 and AD9861-80 Parameter INPUT CLOCK CLKIN Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD20 Mode, Time Required Before Data Latching Edge) Hold Time (HD20 Mode, Time Required ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Electrical AVDD Voltage DRVDD Voltage Analog Input Voltage Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Stresses above those ...
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AD9861 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS SPI_SDO/AUX_SPI_SDO ADC_LO_PWR/AUX_SPI_CS Table 8. Pin Function Descriptions 1 Pin No. Name 1 SPI_DIO (Interp1) 2 SPI_CLK (Interp0) 3 SPI_SDO/AUXSPI_SDO (FD/HD) 4 ADC_LO_PWR/AUX_SPI_CS 5, 31 DVDD 6, 32 DVSS 7, 16, 50, 51, 61 ...
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Pin No. Name 34 AUX_SPI_CLK 35–44 L9–L0 45 AUX3 46 RESET 47 AUX_ADC_REF 48 CLKIN 52 REFB 54, 55 VIN+B, VIN−B 56 VREF 57, 58 VIN−A, VIN+A 60 REFT 62 RxPwrDwn 63 TxPwrDwn 64 SPI_CS 1 Underlined pin names ...
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AD9861 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 4. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone 0 –10 ...
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FREQUENCY (MHz) Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 76 MHz Tone 62 NORMAL POWER @ 50MSPS LOW ...
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AD9861 SNR –5 –10 –15 –20 –25 INPUT AMPLITUDE (dBFS) Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude 62 AVE (–40 ° ...
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FREQUENCY (MHz) Figure 22. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone 0 –10 –20 –30 ...
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AD9861 62 LOW POWER ADC @ 40MSPS ULTRALOW POWER ADC @ 16MSPS 59 NORMAL POWER @ 80MSPS INPUT FREQUENCY (MHz) Figure 28. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR ...
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AVE (+85° AVE (+25° 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) Figure 34. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. AVDD and Temperature AVE (+25°C) ...
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AD9861 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 40. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω ...
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OUTPUT FREQUENCY (MHz) Figure 46. AD9861 Tx Path THD vs. Output Frequency of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load ...
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AD9861 Figure 52 to Figure 57 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The center two carriers are removed from the signal to observe the ...
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Figure 58 to Figure 63 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The center four carriers are removed from the signal to observe the in-band ...
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AD9861 Figure 64 to Figure 69 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The center four carriers are removed from the signal to observe the ...
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TERMINOLOGY Input Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...
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AD9861 THEORY OF OPERATION SYSTEM BLOCK The AD9861 is targeted to cover the mixed-signal front end needs of multiple wireless communication systems. It features a receive path that consists of dual 10-bit receive ADCs, and a transmit path that consists ...
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Rx Path Application Section Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal source. Figure 71 shows this configuration. AD9861 R SERIES VIN+ C SHUNT VIN– R ...
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AD9861 degradation in SNR at a given full-scale input frequency (f due only to aperture jitter (t ), can be calculated with the A following equation: SNR degradation = 20 log [(½) πF In the equation, the rms aperture jitter, ...
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DAC Equivalent Circuits The AD9861 Tx path consisting of dual 10-bit DACs is shown in Figure 73. The DACs integrate a high performance TxDAC core, a programmable gain control through a programmable gain amplifier (TxPGA), coarse gain control, and offset ...
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AD9861 Clock Input Configuration The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry provides the AD9861 with a low jitter clock input that meets the min/max logic levels while ...
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AUXILIARY CONVERTERS The AD9861 contains auxiliary analog-to-digital converters (AuxADCs) and auxiliary digital-to-analog converters (AuxDACs). These auxiliary converters can be used to measure or force system-wide control signals. By default, the auxiliary converters are disabled and powered down. Enabling and controlling ...
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AD9861 Table 10. Configuring AuxADC Reference AuxADC_A Reference AuxADC Ref Enable Configuration [Register 0x17, Bit 1] Buffered PLL_VDD 0 Internal 3 VREF) 1 Internal 2.5 V (2.5 x VREF) 1 Externally forced 0 The AuxADCs can convert ...
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Figure 76 shows a timing diagram of the AuxSPI when it is used to control and access an AuxADC. Figure 77 shows the timing for each of the three AuxADC modes of operation. NORMAL SPI READOUT EXTERNAL START COVERT BIT ...
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AD9861 DIGITAL BLOCK The AD9861 digital block allows the device to be configured in various timing and operation modes. The following sections discuss the flexible I/O interfaces, the clock distribution block, and the programming of the device through mode pins ...
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Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether transmitting or receiving. Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases) Mode Name U10 FD Interleaved Tx ...
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AD9861 • Buffered Tx clock output (from IFACE3 pin) equals 2× the DAC update rate; one rising edge per interleaved Tx sample. Note the following about the Rx path in FD mode: • ADC CLK Div register can be used ...
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Both the U10 and L10 buses are used on the AD9861. The logic level of the Tx/ Rx selector (controlled through the IFACE1 pin) is used to configure the buses for Rx outputs (during Rx operation ...
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AD9861 Table 15. Mode Pin Names and Descriptions Pin Name Description ADC_LO_PWR ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET. Logic low results in ADC operation at nominal power mode. Logic high results in ...
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Configuring with SPI The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 16 shows the required register writes to configure the AD9861 for FD, optional FD, HD20, optional HD20, HD10, optional HD10, ...
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AD9861 SPI Register Map Registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 18. Table 17. Register Map ...
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Table 18. Register Bit Descriptions Register Bit Register 0: General Bit 7: SDIO BiDir (Bidirectional) Bit 6: LSB First Bit 5: Soft Reset Register 1: Clock Mode Bits 7–5: Clk Mode Bit 2: Enable IFACE2 clkout Bit 1: Inv clkout ...
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AD9861 Register Bit Bit 6: RxREF (Power-Down) Bit 5: DiffRef (Power-Down) Bit 4: VREF (Power-Down) Registers 6/7: Rx Path Bit 5: Rx_A Twos Complement/ Rx_B Twos Complement Bit 4: Rx_A Clk Duty/Rx_B Clk Duty Registers 8/9/A: Rx Path Rx Ultralow ...
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Register Bit Bit 4: TxPGA Fast Update (Mode) Register 13: I/O Configuration Bit 7: Tx Twos Complement Bit 6: Rx Twos Complement Bit 5: Tx Inverse Sample Bits 1,0: Interpolation Control Register 14: I/O Configuration Bit 5: Dig Loop On ...
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AD9861 Register Bit Register 17: Auxiliary Converters Bits 7–2: AuxDAC A FS/AuxDAC B FS/AuxDAC C FS Bit 1: AuxADC Ref Enable Bit 0: AuxADC Ref FS Registers 18/19 : AuxADC Bit 7: Start Average AuxADC A/ Start Average AuxADC B ...
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Register Bit Register 23: AuxADC Bits 1,0: AuxADC Clock Div Registers 24, 25, 26: AuxDAC AuxDAC A, B, and C Output Control Word Register 28: AuxDAC Bit 7: Slave Enable Bits 2/1/0: Update C, B, and A Register 29: AuxDAC ...
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AD9861 PROGRAMMABLE REGISTERS The AD9861 contains internal registers that are used to configure the device. A serial port interface provides read/write access to the internal registers. Single-byte or dual-byte transfers are supported as well as MSB first or LSB first ...
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Write Operations The SPI write operation uses the instruction header to config- ure a 1-byte or 2-byte register write using the 2/n1 byte setting. The instruction byte followed by the register data is written serially into the device through the ...
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AD9861 Read Operation The readback of registers can be a single or dual data byte operation. The readback can be configured to use 3-wire or 4-wire and can be formatted with MSB first or LSB first. The instruction header is ...
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CLOCK DISTRIBUTION BLOCK Theory/Description The AD9861 uses a clock distribution block to distribute the timing derived from the input clock (applied to the CLKIN pin, referred to here as CLKIN) to the Rx and Tx paths. There are many options ...
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AD9861 CLKIN ALTERNATE TIMING MODE: REG 0x15, BIT 4 2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0 3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT PATH DIVIDE BY 2: REG ...
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Table 23. Serial Registers Related to the Clock Distribution Block Register Address, Register Name Bit(s) Enable IFACE2 Register 0x01, Bit 2 Inv clkout (IFACE3) Register 0x01, Bit 1 Tx Inverse Sample Register 0x13, Bit 5 Interpolation Control Register 0x13, Bit ...
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AD9861 Table 25 shows typical output delay times for the AD9861 in the various mode configurations. Table 25. AD9861 Rx Data Latch Timing Mode No. Mode Name Optional FD 4 HD20 5 Optional HD20 7 HD10 8 ...
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OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 9.00 BSC SQ 0.60 MAX 49 48 TOP 8.75 VIEW BSC SQ 0.45 0. 0.35 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC ...
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... AD9861 ORDERING GUIDE Model Temperature Range AD9861BCP-50 –40°C to +85°C (Ambient) AD9861BCP-80 –40°C to +85°C (Ambient) AD9861BCPRL-50 –40°C to +85°C (Ambient) AD9861BCPRL-80 –40°C to +85°C (Ambient) AD9861-50EB 25°C (Ambient) AD9861-80EB 25°C (Ambient) Package Description 64-Lead LFCSP 64-Lead LFCSP ...
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NOTES Rev Page AD9861 ...
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AD9861 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03606–0–11/03(0) Rev Page ...