MT9V022IA7ATC Aptina LLC, MT9V022IA7ATC Datasheet - Page 13

• Manufacturer Part Number: MT9V022IA7ATC
• Description: SENSOR IMAGE VGA COLOR 52IBGA
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr
• Series: DigitalClarity®r

Specifications of MT9V022IA7ATC

• Pixel Size: 6µm x 6µm
• Active Pixel Array: 752H x 480V
• Frames Per Second: 60
• Voltage - Supply: 3.3V
• Package / Case: 52-IBGA
• Sensor Image Color Type: Color
• Sensor Image Size Range: 250,920 to 480,000Pixels
• Sensor Image Size: 752x480Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Package Type: IBGA
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1166

Table 5:
PDF:09005aef8201ffc3/Source: 09005aef81ff2525
MT9V022_Product_Brief - Rev. A 1/06 EN
52-Ball IBGA
E7, E8, D7, D8
Numbers
A1, A4
B1, C3
B4, E2
C8, F7
C6, F3
C7, F6
A5
G4
G3
G5
H2
G2
G1
H1
H5
G6
A8
A7
A6
A3
A2
E1
B7
B6
B5
B3
B2
B8
F1
F2
Ball Descriptions (continued)
Only pins D
SER_DATAOUT_N
SHFT_CLKOUT_N
SER_DATAOUT_P
SHFT_CLKOUT_P
Notes: 1. Pin H7 (RSVD) must be tied to GND.
FRAME_VALID
STFRM_OUT
LINE_VALID
STLN_OUT
LVDSGND
LED_OUT
V
OUT
Symbol
VAAPIX
SYSCLK
PIXCLK
ERROR
D
D
D
D
D
D
D
D
D
D
DD
S
D
A
V
V
DATA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
GND
GND
0 through D
DD
AA
LVDS
2. Output Enable (OE) tri-states signals D
3. No connect. These pins must be left floating for proper operation.
5
6
7
8
9
4
3
2
1
0
OUT
9 may be tri-stated.
Ground
Ground
Ground
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Input
Type
I/O
I/O
I/O
NC
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Master clock (26.6 MHz).
Two-wire serial interface data. Connect to V
1.5K resistor even when no other two-wire serial
interface peripheral is attached.
Output in master mode
chip in-phase; input in slave mode.
Output in master mode
slave chip in-phase; input in slave mode.
Asserted when D
Asserted when D
Parallel pixel data output 5.
Parallel pixel data output 6.
Parallel pixel data output 7.
Parallel pixel data output 8
Parallel pixel data output 9.
Error detected. Directly OR with STEREO ERROR FLAG
and PIXEL ERROR FLAG.
LED strobe output.
Parallel pixel data output 4.
Parallel pixel data output 3.
Parallel pixel data output 2.
Parallel pixel data output 1.
Parallel pixel data output 0.
Pixel clock out. D
clock.
Output shift CLK (differential negative).
Output shift CLK (differential positive).
Serial data out (differential negative).
Serial data out (differential positive).
Digital power 3.3V.
Analog power 3.3V.
Pixel power 3.3V.
Dedicated power for LVDS pads.
Dedicated GND for LVDS pads.
Digital GND.
Analog GND.
No connect.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
0-D
OUT
OUT
OUT
OUT
Description
data is valid.
data is valid.
is valid on rising edge of this
9. No other signals are tri-stated with OE.
—
—
start line sync to drive slave
start frame sync to drive a
Electrical Specifications
©2006 Micron Technology, Inc. All rights reserved.
DD
with
Notes
3