CYII4SM6600AB-QWC Cypress Semiconductor Corp, CYII4SM6600AB-QWC Datasheet - Page 26

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CYII4SM6600AB-QWC

Manufacturer Part Number
CYII4SM6600AB-QWC
Description
IC SENSOR IMAGE MONO 68-LCC
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Datasheet

Specifications of CYII4SM6600AB-QWC

Pixel Size
3.5µm x 3.5µm
Active Pixel Array
2210H x 3002V
Frames Per Second
5
Voltage - Supply
2.5V, 3.3V
Package / Case
68-LCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
ADC Timing
Two Analog Outputs
Figure 26
(in case of internal clock, the clock is half the SYS_CLOCK).
T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total pipeline delay of four pixels.
One Analog Output
Figure 27
T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
Document Number: 001-02366 Rev. *G
shows the timing of the ADC using two analog outputs. Internally, the ADCs sample on the falling edge of the ADC_CLOCK
shows the timing of the ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK.
Figure 26. ADC Timing using Two Analog Outputs
Figure 27. ADC Timing using One Analog Output
IBIS4-6600 CYII4SM6600AB
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