TGF4118 TriQuint, TGF4118 Datasheet
TGF4118
Specifications of TGF4118
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TGF4118 Summary of contents
Page 1
... Nominal Pout of 9.0 Watts at 2.3 GHz • Nominal PAE of 53% at 2.3 GHz • Nominal Gain of 11 2.3 GHz • Die Size 36.0 x 81.0 x 4.0 mils (0.914 x 2.057 x 0.102 mm) TGF4118-EPU RF Performance 2.3 GHz 1.69 A and T 50 Pout 48 PAE ...
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... TGF4118-EPU RF Performance for 2.3 GHz, and T Quiescent Id is 1.74 A (Vg = -1.1 V), 1.37 A (Vg = -1.3 V), and 1.02 A (Vg = -1.5 V) 130 120 110 100 Pout - TriQuint Semiconductor Texas Phone: 972 994-8465 Input Power (dBm) Fax 972 994-8504 = 25° Tch - ...
Page 3
... TGF4118-EPU RF Performance for 2.3 GHz, and T Quiescent Id is 1.69 A (Vg = -1.1 V), 1.38 A (Vg = -1.3 V), and 1.06 A (Vg = -1.5 V) 140 130 120 110 100 - TriQuint Semiconductor Texas Phone: 972 994-8465 Pout Input Power (dBm) Fax 972 994-8504 = 25° Tch 37 36 ...
Page 4
... TGF4118-EPU RF Performance for 2.3 GHz, and T Quiescent Id is 1.66 A (Vg = -1.1 V), 1.39 A (Vg = -1.3 V), and 1.09 A (Vg = -1.5 V) 160 150 140 130 120 110 100 90 Pout - TriQuint Semiconductor Texas Phone: 972 994-8465 Input Power (dBm) Fax 972 994-8504 = 25°C ...
Page 5
... DC Characteristics for the TGF4118-EPU DC probe Parameters IDSS Drain Saturation Current GM Transconductance VP Pinch Off Voltage BVGS Breakdown Voltage Gate-Source BVGD Breakdown Voltage Gate-Drain -2. 0.25 steps Absolute Maximum Ratings Drain-to-source Voltage, Vds..............................…………………………………………..........12 V Gate-to-source Voltage, Vgs..................… ...
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... TGF4118-EPU Linear Model Vds = 7 V and Ids = 1. 25°C FET Elements Lg = .00176 0.42115 Ω Rgs = 5447 Ω .05082 Ω Cgs = 18.82602 pF Cdg = 1.03674 pF Rdg = 13600 Ω 0.06265 Ω 0.00869 nH Rds = 6.40925 Ω Cds = 3.72019 0.01831 Ω 0.00195 nH VCCS Parameters M = 2.04398 1E19 ...
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... Thermal Model of TGF4118-EPU Predicted Channel Temperature vs Base Plate Temperature With a .020" CM15 (15/85 Copper Molybdenum) carrier plate solder attached 250 240 230 220 210 200 190 180 170 160 150 140 130 120 110 100 2.052 + 6.796 Pd + 0.1465 x (Predicted Channel Temperature equation for the given assembly stack up) This model assumes perfect solder connections (no voids) between the FET and the carrier plate ...
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... Mechanical Drawing of TGF4118-EPU 81.0 (2.057) 76.3 (1.938) 65.3 (1.659) 48.8 (1.239) 32.2 (0.819) 15.7 (0.399) 4.7 (0.119) 0.0 0.0 Alternate gate pad Units: mils (mm) Thickness: 4.0 (0.10) Gate pad sizes are 4.0 x 4.0 (0.10 x 0.10) Drain pad sizes are 4.7 x 14.5 (0.12 x 0.37) A minimum of four gate bonds and eight drain bonds is recommended for operation ...
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... Application circuit for the TGF4118-EPU at 2.3 GHz The FET is soldered using AuSn solder at 300 C for 30 secs. Input and Output matching networks are 0.381 mm ZrSn Tioxide substrates (Er = 38). The design load impedance is between 4 Ω and 5 Ω with the 6 pF output capacitance of the FETincluded in the output network. For further explanation refer to the application note “ ...