LTC3550EDHC-1#TR Linear Technology, LTC3550EDHC-1#TR Datasheet - Page 17

• Manufacturer Part Number: LTC3550EDHC-1#TR
• Description: IC,Battery Management,CMOS,LLCC,16PIN,PLASTIC
• Manufacturer: Linear Technology
• Type: Battery Chargerr

Specifications of LTC3550EDHC-1#TR

• Battery Type: Li-Ion
• Output Current: 800mA
• Output Voltage: 4.2V
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Using Ceramic Input and Output Capacitors
Higher capacitance values, lower cost ceramic capacitors
are now becoming available in smaller case sizes. Their
high ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. Because the
LTC3550-1’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3550-1 circuits: V
and I
the effi ciency loss at very low load currents whereas the
I
load currents. In a typical effi ciency plot, the effi ciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 3.
APPLICATIO S I FOR ATIO
1. The V
2
R loss dominates the effi ciency loss at medium to high
Effi ciency = 100% – (L1 + L2 + L3 + ...)
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from V
dQ/dt is the current out of V
2
R losses. The V
CC
quiescent current is due to two components:
U
CC
quiescent current loss dominates
U
CC
CC
to ground. The resulting
that is typically larger
W
CC
quiescent current
U
2. I
The R
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
and multiply the result by the square of the average output
current. Other losses including C
tive losses and inductor core losses generally account for
less than 2% total additional loss.
internal switches, R
continuous mode, the average output current fl owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
(DC) as follows:
than the DC bias current. In continuous mode, I
= f(Q
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
thus their effects will be more pronounced at higher
supply voltages.
R
2
SW
R losses are calculated from the resistances of the
DS(ON)
T
= (R
+ Q
0.00001
0.0001
0.001
DS(ON)TOP
0.01
Figure 3. Power Lost vs Load Current
B
0.1
for both the top and bottom MOSFETs can
1
) where Q
0.1
)(DC) + (R
1
SW
LOAD CURRENT (mA)
T
2
R losses, simply add R
, and external inductor R
and Q
10
DS(ON)
B
DS(ON)BOT
IN
are the gate charges of
and C
100
LTC3550-1
and the duty cycle
3550-1 F03
OUT
)(1 – DC)
1000
ESR dissipa-
SW
GATECHG
17
CC
to R
L
35501f
and
. In
L