LTC4215CGN#TR Linear Technology, LTC4215CGN#TR Datasheet - Page 20

• Manufacturer Part Number: LTC4215CGN#TR
• Description: IC,Power Control/Management,CMOS,SSOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4215CGN#TR

• Linear Misc Type: Positive Low Voltage
• Family Name: LTC4215
• Package Type: SSOP N
• Operating Supply Voltage (min): 2.9V
• Operating Supply Voltage (max): 15V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

LTC4215/LTC4215-2
APPLICATIONS INFORMATION
The transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a Write Word command, the second data byte
is acknowledged by the LTC4215 but ignored, as shown
in Figure 8.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit
set to zero, as shown in Figure 9. The addressed LTC4215
acknowledges this and then the master sends a command
byte which indicates which internal register the master
20
S
ADDRESS
1 0 a4:a0
S
S
Figure 11. LTC4215 Serial Bus SDA Alert Response Protocol
Figure 10. LTC4215 Serial Bus SDA Read Word Protocol
Figure 8. LTC4215 Serial Bus SDA Write Word Protocol
Figure 7. LTC4215 Serial Bus SDA Write Byte Protocol
ADDRESS
ADDRESS
Figure 9. LTC4215 Serial Bus SDA Read Byte Protocol
1 0 a4:a0
1 0 a4:a0
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
ADDRESS
W
1 0 a4:a0
0
A
0
W
W
0
0
X X X X X b2:b0
S
A
A
0
0
COMMAND
0 0 0 1 1 0 0
W
RESPONSE
0
ADDRESS
X X X X X b2:b0
X X X X X b2:b0
ALERT
COMMAND
COMMAND
A
0
X X X X X b2:b0
COMMAND
R
1
A
0
A
0
S
A
A
0
0
1 0 a4:a0 0
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
ADDRESS
ADDRESS
wishes to read. The LTC4215 acknowledges this and then
latches the lower three bits of the command byte into its
internal Register Address pointer. The master then sends
a repeated START condition followed by the same seven
bit address with the R/W bit now set to one. The LTC4215
acknowledges and send the contents of the requested
register. The transmission is ended when the master
sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4215 repeats the requested register as
the second data byte.
1 0 a4:a0
DEVICE
S
b7:b0
DATA
A
0
ADDRESS
1 0 a4:a0
b7:b0
DATA
A
0
R A
1 0
A P
1
4215 F11
X X X X X X X X
4215 F07
A P
0
R A
1 0
DATA
b7:b0
DATA
DATA
b7:b0 1
A
0
DATA
b7:b0
A P
0
A P
4215 F08
4215 F10
A P
1
4215 F11
4215fe