LTC4215CUFD Linear Technology, LTC4215CUFD Datasheet - Page 21
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LTC4215CUFD
Manufacturer Part Number
LTC4215CUFD
Description
IC,Power Control/Management,CMOS,LLCC,24PIN,PLASTIC
Manufacturer
Linear Technology
Datasheet
1.LTC4215CUFD.pdf
(28 pages)
Specifications of LTC4215CUFD
Linear Misc Type
Positive Low Voltage
Family Name
LTC4215
Package Type
QFN EP
Operating Supply Voltage (min)
2.9V
Operating Supply Voltage (max)
15V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Product Depth (mm)
4mm
Product Length (mm)
5mm
Mounting
Surface Mount
Pin Count
24
Lead Free Status / Rohs Status
Not Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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LT
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Manufacturer:
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Part Number:
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Manufacturer:
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Part Number:
LTC4215CUFD-1
Manufacturer:
LT
Quantity:
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Manufacturer:
LINEAR/凌特
Quantity:
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Part Number:
LTC4215CUFD-2#PB
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS INFORMATION
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the ALERT pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215 responds with its address on the
SDA line and then release ALERT as shown in Figure 11.
Table 1A. LTC4215 Device Addressing (UH24 Package)
Alert Response
DESCRIPTION
Mass Write
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0
1
2
3
4
5
6
7
8
9
ADDRESS
DEVICE
BE
19
80
82
84
86
88
8A
8C
8E
90
92
94
96
98
9A
9C
9E
A0
A2
A4
A6
A8
AA
AC
AE
B0
B2
B4
h
7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
DEVICE ADDRESS
4
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
The ALERT line is also released if the device is addressed
by the bus master. The ALERT signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
3
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
2
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
LTC4215/LTC4215-2
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
ADR2
NC
NC
NC
NC
NC
NC
NC
NC
NC
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
ADDRESS PINS
LTC4215UH
ADR1
NC
NC
NC
NC
NC
NC
NC
NC
NC
X
X
H
L
H
L
L
H
L
H
L
L
H
L
H
L
L
H
H
H
21
ADR0
NC
NC
NC
NC
NC
NC
NC
NC
NC
X
X
L
H
L
H
H
L
H
L
H
H
L
H
L
H
H
L
L
L
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