LTC4245CUHF#TR Linear Technology, LTC4245CUHF#TR Datasheet - Page 22

• Manufacturer Part Number: LTC4245CUHF#TR
• Description: IC,Power Control/Management,CMOS,LLCC,38PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4245CUHF#TR

• Family Name: LTC4245
• Package Type: QFN EP
• Operating Supply Voltage (min): 2.25/4.25/10.2/-10.2V
• Operating Supply Voltage (max): 0/10/20/-20V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 5mm
• Product Length (mm): 7mm
• Mounting: Surface Mount
• Pin Count: 38
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4245
Q5. The CPCI specifi cation assumes that there is a diode
to 3.3V on the circuit that is driving the BD_SEL# pin. If
the BD_SEL# pin is being driven high, the actual voltage
on the pin will fall to approximately 3.9V from 5V. This is
still above the threshold of the LTC4245 BD_SEL# pin, but
low enough for Q5 to pull ⎯ O ⎯ E high. Since the bus switch is
powered off an early power plane, a 100Ω resistor should
be placed in series with its V
When the plug-in card is removed from the backplane,
the BD_SEL# connection is broken fi rst, and the BD_SEL#
voltage pulls up to 5V. This causes Q5 to turn off, which
re-enables the bus switch, and the precharge resistors are
again connected to the PRECHARGE pin for the remainder
of the extraction process.
Data Converter
The LTC4245 incorporates an 8-bit data converter that
continuously converts thirteen different channels. Twelve
of these channels are used for each supply’s input, current
sense and output voltages. One of the three GPIO pins can
be multiplexed to the thirteenth channel using bits G6 and
G7. The results from each conversion are stored in registers
I through U and are updated once every 665ms. Since the
ADC is powered off INTV
it is not possible to convert 12V
ADC and serial bus are held in reset.
The ADC can also measure a particular channel on-demand.
First the ADC needs to be taken out of it’s free-running mode
by setting control bit C7. The ADC enters a quiescent state,
which is indicated by the ADC busy bit, A7, going to logic
zero. Writing the address of a channel to ADCADR register
triggers the start of one conversion of that channel’s volt-
age. Bit A7 goes high to indicate ADC activity. It goes low
again after the ADC fi nishes the conversion and writes the
result to the channel’s data register. The same or different
address can be written again to start a new conversion.
The quiescent state of the ADC can also be used to read
and write from the ADC data registers for software test-
ing purposes. Resetting bit C7 allows the ADC to again
start cycling through the thirteen channels starting with
the fi rst one.
22
U
CC
U
, which is derived from 12V
DD
.
IN
below about 8V as the
W
U
IN
,
Digital Interface
The LTC4245 communicates with a bus master using a
2-wire interface compatible with the I
an I
The LTC4245 is a read-write slave device and supports
SMBus Read Byte, Write Byte, Read Word and Write Word
commands. The second word in a Read Word command
will be identical to the fi rst word. The second word in a
Write Word command is ignored. The data formats for
these commands are shown in Figures 12 to 15.
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has fi nished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission.
I
Thirty-two distinct bus addresses are confi gurable using
the two-state ADR0, ADR1 pins and the three-state ADR2,
ADR3 pins. Table 5 shows the correspondence between
pin states and addresses. Note that address bits B7 and B6
are internally confi gured to (01)b. The fi rst 16 addresses
are compatible with the geographic addressing scheme
used in CompactPCI to encode physical slot addresses.
In addition, the LTC4245 will respond to two special ad-
dresses. Address (0010 111)b is a mass write address
used to write to all LTC4245, regardless of their individual
address settings. The mass write can be masked by setting
register bit C5 to zero. Address (0001 100)b is the SMBus
Alert Response Address. If the LTC4245 is pulling low on
the ALERT# pin, it will acknowledge this address using
the SMBus Alert Response Protocol.
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last byte
of data was received. The transmitter always releases the
2
C Device Addressing
2
C extension for low power devices.
2
C bus and the SMBus,
4245fa