LTC4259ACGW-1 Linear Technology, LTC4259ACGW-1 Datasheet - Page 4

• Manufacturer Part Number: LTC4259ACGW-1
• Description: IC,Power Control/Management,CMOS,SOP,36PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1

• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

LTC4259A-1
temperature range, otherwise specifications are at T
(Note 6).
SYMBOL
t
t
DC
t
t
I
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2: DGND and AGND should be tied together in normal operation.
Note 3: An internal clamp limits the GATE pins to a minimum of 12V above
V
Note 4: When a port powers on or off, the transient voltage on the port
couples through C
protection circuitry to withstand transient currents of up to 80mA for 5ms.
As long as the absolute value of the current remains below 80mA, the
LTC4259A-1 will keep the voltage at the DETECT n pin within the absolute
maximum voltage range. A properly sized R
less than 60mA.
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
ELECTRICAL CHARACTERISTICS
4
START
ICUT
DIS
VMIN
2
SCLK
1
2
3
4
5
6
7
8
r
f
FLTINT
STOPINT
ARAINT
EE
C Timing
CLMAX
. Driving this pin beyond the clamp may damage the part.
PARAMETER
Maximum Current Limit Duration During
Port Start-Up
Maximum Current Limit Duration After
Port Start-Up
Maximum Current Limit Duty Cycle
Disconnect Delay
DC Disconnect Minimum Pulse
Width Sensitivity
Clock Frequency
Bus Free Time
Start Hold Time
SCL Low Time
SCL High Time
Data Hold Time
Data Set-Up Time
Start Set-Up Time
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
DET
(Figure 18). The LTC4259A-1 contains internal
DET
should limit the current to
t
t
t
t
Reg16h = 00h
t
t
t
t
V
(Note 11)
(Note 11)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
Figure 6 (Notes 11, 12)
(Notes 11, 12, 13)
(Notes 11, 12, 13)
(Notes 11, 12)
CONDITIONS
t
t
t
t
ICUT1
ICUT1
ICUT1
ICUT1
DIS1
DIS1
DIS1
DIS1
START1
START1
START1
START1
SENSE n
A
= 0, t
= 0, t
= 1, t
= 1, t
= 25°C. AGND = DGND = 0V, V
= 0, t
= 0, t
= 1, t
= 1, t
= 0, t
= 0, t
= 1, t
= 1, t
– V
DIS0
DIS0
DIS0
DIS0
The
ICUT0
ICUT0
ICUT0
ICUT0
EE
START0
START0
START0
START0
> 5mV, V
= 0 (Figures 4, 5)
= 1 (Figures 4, 5)
= 0 (Figures 4, 5)
= 1 (Figures 4, 5)
●
= 0 (Figure 3)
= 1 (Figure 3)
= 0 (Figure 3)
= 1 (Figure 3)
denotes the specifications which apply over the full operating
= 0 (Figure 3)
= 1 (Figure 3)
= 0 (Figure 3)
= 1 (Figure 3)
Note 6: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground (AGND and DGND)
unless otherwise specified.
Note 7: The LTC4259A-1 is designed to maintain a port voltage of –46.6V
to –57V. The V
diode, MOSFET and sense resistor.
Note 8: V
indirectly by measuring the DETECT n pin current while classifying a short.
Note 9: The LTC4259A-1 implements overload current detection per IEEE
802.3af. The minimum overload current (I
voltage; I
LTC4259A-1 should maintain port voltage above –46.6V.
Note 10: Unless otherwise specified, AC disconnect specifications require
the following conditions: the DETECT pin is connected to the port as
shown in Figure 1, a valid sine wave is applied to OSCIN, the OSCFAIL bit
is cleared and the AC Disconnect Enable bits are set.
Note 11: Guaranteed by design, not subject to test.
Note 12: Values measured at V
Note 13: If fault occurs during an I
pulled down until a stop condition is present on the I
OUT n
= –48V (Figure 4)
CUT_MIN
EE
supply current, while classifying a short, is measured
EE
DD
supply voltage range accounts for the drop across the
= 15.4W/V
= 3.3V, V
PORT_MIN
ILD
EE
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
= –48V unless otherwise noted
and V
2
C transaction, the INT pin will not be
MIN
. An IEEE compliant system using the
100
200
100
200
300
150
600
600
600
150
200
600
600
5.8
1.3
1.3
50
25
50
25
75
20
20
20
60
20
IHD
CUT
.
) is dependent on port
0.02
TYP
120
240
120
240
360
180
720
6.3
60
30
60
30
90
2
C bus.
MAX
140
280
140
280
400
100
200
800
400
300
150
150
200
300
6.7
70
35
70
35
1
4259a1fa
UNITS
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%