CS1W-SCB41-V1 Omron, CS1W-SCB41-V1 Datasheet - Page 5

• Manufacturer Part Number: CS1W-SCB41-V1
• Description: BOARD,RS232C,RS-422A/485
• Manufacturer: Omron

Specifications of CS1W-SCB41-V1

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Use the improved SYSMAC CS1 PLCs to scale advanced systems to the optimum size.
1
The evolution of the
SYSMAC CS1 is
accelerating advances
in the production site.
Previous CS1
Previous CS1
Previous CS1
Faster Instruction Execution and Faster Overall Performance
System Bus Baud Rate Doubled
Reduced Variation in Cycle Time During Data Processing
In addition to further improvements to the
instruction execution engine, which is the
core of overall PLC performance, the high-
speed RISC chip has been upgraded to
realize the fastest instruction execution
performance in the industry. Also, the
The figures above are for high-speed, general-purpose PLCs with
interchangeable boards.
The PCMIX is the average number of instructions that can be executed
in 1 µs and expresses the over execution performance of the ladder
program. This unit was conceived to allow comparing the performance
of PLCs from different manufacturers using a common metric.
With normal I/O refresh, 1-ms pulses are not lost even for large-
capacity (e.g., 30-Kstep) programs. This allows use in applications
requiring a high working accuracy, such as molding equipment.
The data transfer rate between the CPU
Unit and certain Units has been doubled to
further improve total system performance.
Instructions that require long execution
time, such as table data processing
instructions and text string processing
instructions, are processed over multiple
New CS1
New CS1
New CS1
Common Processing: 1.6 Times Faster
models
PCMIX Value: 3 Times Higher
models
Cycle Time: 2.5 to 4.8 Times Shorter
(Cycle time for 128 inputs and 128 outputs)
models
models
models
models
Table data/
text string
processing
Basic instructions only: 38 Ksteps/ms
Including special instructions:
22 Ksteps/ms
5
The cycle is temporarily
extended when the instruction
is executed.
Long
Long
Long
execution
execution
execution
time
time
time
Variation
0.3 ms
0.5 ms
8 Ksteps/ms
16
Previous CS1
Previous CS1
Previous CS1
new models have a mode where
instruction execution and peripheral
processing are processed in parallel,
enabling balanced improvements in overall
speed.
cycles to minimize variations in cycle time
and maintain stable I/O response.
The development of a special LSI to execute instructions and use of a
high-speed RISC chip enable high-speed processing at the CPU.
Programs consisting mainly of basic instructions are processed at
ultrahigh speed.
Cycle time overhead due to program structuring is minimized.
New CS1
New CS1
New CS1
Table data/
text string
processing
CS1 CPU Bus Units
CS1 I/O Units
CS1 Special I/O Units
models
models
models
LD Instruction Processing Speed:
2 Times Faster
OUT Instruction Processing Speed:
8 Times Faster
Subroutine Processing Speed:
17.6 Times Faster
models
models
models
Background processing performed over several
cycles to limit the impact on cycle time and thus
reduce variation in cycle time.
2.1 µ s
Only start of
processing
designated.
20 ns
doubled
Baud rate
System bus
20 ns
CPU Unit
40 ns
170 ns
37 µ s
251