FDG6303N Fairchild Semiconductor, FDG6303N Datasheet - Page 2

• Manufacturer Part Number: FDG6303N
• Description: IC FET DGTL N-CHAN DUAL SC70-6
• Manufacturer: Fairchild Semiconductor

Specifications of FDG6303N

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 450 mOhm @ 500mA, 4.5V
• Drain To Source Voltage (vdss): 25V
• Current - Continuous Drain (id) @ 25° C: 500mA
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 2.3nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 50pF @ 10V
• Power - Max: 300mW
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Configuration: Dual
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.45 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 1.45 S
• Drain-source Breakdown Voltage: 25 V
• Gate-source Breakdown Voltage: - 0.5 V to 8 V
• Continuous Drain Current: 0.5 A
• Power Dissipation: 300 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDG6303NTR

Notes:
1. R
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Electrical Characteristics
Symbol
OFF CHARACTERISTICS
BV
I
I
ON CHARACTERISTICS
V
R
I
g
DYNAMIC CHARACTERISTICS
C
C
C
SWITCHING CHARACTERISTICS
t
t
t
t
Q
Q
Q
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
V
DSS
GSS
D(ON)
D(on)
r
D(off)
f
S
FS
BV
GS(th)
V
SD
DS(ON)
iss
oss
rss
g
gs
gd
by design while R
DSS
GS(th)
JA
DSS
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
/ T
/ T
J
J
Parameter
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
Gate - Body Leakage Current
Gate Threshold Voltage
Gate Threshold Voltage Temp.Coefficient
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Maximum Continuous Source Current
Drain-Source Diode Forward Voltage
CA
is determined by the user's board design. R
(Note 2)
(Note 2)
(T
A
JA
= 25
= 415
O
C/W on minimum pad mounting on FR-4 board in still air.
O
C unless otherwise noted )
Conditions
V
I
V
V
V
I
V
V
V
V
V
V
V
V
V
V
D
D
f = 1.0 MHz
GS
DS
GS
DS
GS
GS
GS
DS
DS
DD
GS
DS
GS
GS
= 250 µA, Referenced to 25
= 250 µA, Referenced to 25
= 20 V, V
= V
= 5 V, I
= 10 V, V
= 5 V, I
= 0 V, I
= 8 V, V
= 4.5 V, I
= 2.7 V, I
= 2.7 V, V
= 5 V, I
= 4.5 V, R
= 4.5 V
= 0 V, I
GS
, I
D
D
D
D
D
S
DS
= 0.5 A
= 0.25 A
= 250 µA
= 250 µA
= 0.5 A,
D
D
GS
GS
= 0.5 A,
DS
GEN
= 0 V
= 0.5 A
= 0.2 A
= 0 V
= 0 V,
= 5 V
= 50
(Note 2)
T
T
J
J
= 55°C
=125°C
o
o
C
C
0.65
Min
0.5
25
0.34
0.55
0.44
1.45
1.64
0.38
0.45
Typ
-2.6
0.8
8.5
0.8
26
50
28
17
13
9
3
Max
0.45
0.77
0.25
100
1.5
0.6
2.3
1.2
10
18
30
25
1
6
JC
FDG6303N Rev.F
is guaranteed
mV/
mV/
Units
µA
µA
nA
nC
nC
nC
ns
ns
ns
ns
o
o
V
V
A
S
pF
pF
pF
A
V
C
C