FDC6320C Fairchild Semiconductor, FDC6320C Datasheet

MOSFET N/P-CH DUAL 25V SSOT6

FDC6320C

Manufacturer Part Number
FDC6320C
Description
MOSFET N/P-CH DUAL 25V SSOT6
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FDC6320C

Fet Type
N and P-Channel
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
4 Ohm @ 400mA, 4.5V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
220mA, 120mA
Vgs(th) (max) @ Id
1.5V @ 250µA
Gate Charge (qg) @ Vgs
0.4nC @ 4.5V
Input Capacitance (ciss) @ Vds
9.5pF @ 10V
Power - Max
700mW
Mounting Type
Surface Mount
Package / Case
6-SSOT, SuperSOT-6
Configuration
Dual
Transistor Polarity
N and P-Channel
Resistance Drain-source Rds (on)
4 Ohm @ 4.5 V @ N Channel
Forward Transconductance Gfs (max / Min)
0.2 S, 0.135 S
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
8 V @ N Channel or - 8 V @ P Channel
Continuous Drain Current
0.22 A @ N Channel or 0.12 A @ P Channel
Power Dissipation
900 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC6320C
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Company:
Part Number:
FDC6320C
Quantity:
5 000
Part Number:
FDC6320C-NL
Manufacturer:
SUNRISE
Quantity:
20 000
© 1997 Fairchild Semiconductor Corporation
FDC6320C
Dual N & P Channel , Digital FET
General Description
Symbol
V
V
I
P
T
ESD
THERMAL CHARACTERISTICS
R
R
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
D
Absolute Maximum Ratings
J
DSS
GSS
, I
D
,T
JA
J
C
O
STG
, V
, V
SOT-23
CC
IN
Parameter
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current
Maximum Power Dissipation
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
SuperSOT
TM
-6
- Continuous
- Pulsed
T
A
= 25
o
C unless other wise noted
SuperSOT
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1)
TM
-8
Features
N-Channel
N-Ch 25 V, 0.22 A, R
P-Ch 25 V, -0.12 A, R
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
SO-8
0.22
0.5
25
8
4
6
5
0.7
-55 to 150
140
0.9
60
6
SOT-223
DS(ON)
DS(ON)
GS(th)
= 5
= 13
P-Channel
< 1.5 V.
-0.12
-0.5
-25
-8
@ V
@ V
3
2
1
GS
October 1997
GS
= 2.7 V.
= -2.7 V.
SOIC-16
FDC6320C.Rev C
Units
°C/W
°C/W
kV
W
°C
V
V
A

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FDC6320C Summary of contents

Page 1

... Replace NPN & PNP digital transistors. TM SO-8 SuperSOT - unless other wise noted A N-Channel 25 0.22 0.5 (Note 1a) (Note 1b) (Note 1a) (Note 1) October 1997 = 2.7 V. DS(ON -2.7 V. DS(ON) GS < 1.5 V. GS(th) SOIC-16 SOT-223 P-Channel - -0.12 -0.5 0.9 0.7 -55 to 150 6 140 60 Units °C kV °C/W °C/W FDC6320C.Rev C ...

Page 2

... P-Ch -100 o N-Ch -2 P-Ch 1.9 N-Ch 0.65 0.85 1.5 P-Ch -0.65 -1 -1.5 N-Ch 3 =125°C 6 3.1 4 P-Ch 10 =125°C J 7.9 10 N-Ch 0.2 P-Ch -0.05 N-Ch 0.2 P-Ch 0.135 N-Ch 9.5 P-Ch 11 N-Ch 6 P-Ch 7 N-Ch 1.3 P-Ch 1.4 Units µA µ FDC6320C.Rev C ...

Page 3

... Type Min Typ Max Units N- P- N- P-Ch 7.4 15 N- N-Ch 0.29 0.4 nC P-Ch 0.23 0.32 N-Ch 0.105 nC P-Ch 0.12 N-Ch 0.045 nC P-Ch 0.03 N-Ch 0.5 A P-Ch -0.5 N-Ch 0.97 1.3 V P-Ch -1 -1.3 is guaranteed by JC FDC6320C.Rev C ...

Page 4

... I , DRAIN CURRENT (A) D Drain Current and Gate Voltage 0.2A D 25°C 125°C 2 GATE TO SOURCE VOLTAGE (V) GS Gate-To- Source Voltage 125°C J 25°C -55° BODY DIODE FORWARD VOLTAGE (V) SD Variation with Source Current and Temperature. FDC6320C.Rev C 0 ...

Page 5

... Figure 9. Maximum Safe Operating Area. (continued 0. iss 3 C oss rss 0.05 Figure 8. Gate Charge Characteristics 0. Figure 10. Single Pulse Maximum Power V = 5.0V DS 0.1 0.15 0.2 0.25 0 GATE CHARGE (nC SINGLE PULSE R =See note 25° SINGLE PULSE TIME (SEC) Dissipation. FDC6320C.Rev C 0.35 100 300 ...

Page 6

... Drain Current and Gate Voltage -0.05A 25°C A 125 ° ,GATE TO SOURCE VOLTAGE (V) GS Gate-To- Source Voltage 125°C J 25°C -55°C 0 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature. -3.5 -4.5 0 1.2 FDC6320C.Rev C ...

Page 7

... C rss 0.01 Figure 20. Single Pulse Maximum Power 0.01 0 TIME (sec -2.7V GS =See Note DRAIN-SOURCE VOLTAGE (V) DS SINGLE PULSE R =See note 25° SINGLE PULSE TIME (SEC) Dissipation. R ( See Note 1b JA P(pk ( Duty Cycle 100 300 FDC6320C.Rev C 40 100 300 ...

Page 8

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...

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