FDMC8200 Fairchild Semiconductor, FDMC8200 Datasheet - Page 8

MOSFET 2N-CH 30V 8A/12A POWER33

FDMC8200

Manufacturer Part Number
FDMC8200
Description
MOSFET 2N-CH 30V 8A/12A POWER33
Manufacturer
Fairchild Semiconductor
Series
PowerTrench®r
Datasheet

Specifications of FDMC8200

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
20 mOhm @ 6A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
8A, 12A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
10nC @ 10V
Input Capacitance (ciss) @ Vds
660pF @ 15V
Power - Max
700mW, 900mW
Mounting Type
Surface Mount
Package / Case
8-MLP, Power33
Configuration
Dual
Transistor Polarity
Dual N-Channel
Resistance Drain-source Rds (on)
16 mOhms, 7.3 mOhms
Forward Transconductance Gfs (max / Min)
29 S, 56 S
Drain-source Breakdown Voltage
30 V
Continuous Drain Current
18 A
Power Dissipation
1.9 W, 2.2 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Module Configuration
Dual
Continuous Drain Current Id
8A
Drain Source Voltage Vds
30V
On Resistance Rds(on)
20mohm
Rds(on) Test Voltage Vgs
10V
Threshold Voltage Vgs Typ
2.3V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FDMC8200TR

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Part Number
Manufacturer
Quantity
Price
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FDMC8200
Manufacturer:
FAIRCHILD/ON
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FDMC8200
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Part Number:
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FDMC8200
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Part Number:
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Manufacturer:
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FDMC8200 Rev.A1
©2009 Fairchild Semiconductor Corporation
Typical Characteristics (Q2 N-Channel)
0.01
100
0.1
10
10
8
6
4
2
0
Figure 19. Gate Charge Characteristics
1
1000
0.01
100
0
0.5
10
10
1
I
D
Figure 21. Forward Bias Safe
= 9 A
-4
SINGLE PULSE
T
R
T
THIS AREA IS
LIMITED BY r
J
θ
C
JA
= MAX RATED
= 25
3
= 145
V
V
DS
0.1
DD
o
C
, DRAIN to SOURCE VOLTAGE (V)
Operating Area
= 10 V
Q
o
C/W
g
, GATE CHARGE (nC)
DS(on)
6
V
10
DD
-3
= 15 V
1
9
Figure 22. Single Pulse Maximum Power Dissipation
V
DD
12
= 20 V
10
10
-2
15
100 us
10 ms
100 ms
10 s
DC
1 ms
1 s
100200
t, PULSE WIDTH (s)
18
10
-1
T
J
8
= 25 °C unless otherwise noted
2000
1000
100
50
40
30
20
10
1
Figure 22. Maximum Continuous Drain
10
0
0.1
25
Figure 20. Capacitance vs Drain
Limited by Package
f = 1 MHz
V
GS
V
GS
= 0 V
= 4.5 V
V
50
DS
Current vs Case Temperature
to Source Voltage
, DRAIN TO SOURCE VOLTAGE (V)
T
c
10
,
V
CASE TEMPERATURE (
GS
V
GS
= 10 V
75
= 10 V
1
100
100
SINGLE PULSE
R
T
A
θ
JA
= 25
= 145
R
o
C )
o
θ
JC
C
125
www.fairchildsemi.com
o
10
= 4
C/W
C
C
C
o
C/W
rss
oss
iss
1000
150
30

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