NTHC5513T1 ON Semiconductor, NTHC5513T1 Datasheet - Page 8

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NTHC5513T1

Manufacturer Part Number
NTHC5513T1
Description
MOSFET N/P-CH 20V 2.1A CHIPFET
Manufacturer
ON Semiconductor
Datasheet

Specifications of NTHC5513T1

Fet Type
N and P-Channel
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
80 mOhm @ 2.9A, 4.5V
Drain To Source Voltage (vdss)
20V
Current - Continuous Drain (id) @ 25° C
2.9A, 2.2A
Vgs(th) (max) @ Id
1.2V @ 250µA
Gate Charge (qg) @ Vgs
4nC @ 4.5V
Input Capacitance (ciss) @ Vds
180pF @ 10V
Power - Max
1.1W
Mounting Type
Surface Mount
Package / Case
8-ChipFET™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
NTHC5513T1OS

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Figure 22. This is sufficient for low power dissipation
MOSFET
performance requires a greater copper pad area, particularly
for the drain leads.
Figure 23 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
The basic pad layout with dimensions is shown in
The minimum recommended pad pattern shown in
0.457
0.018
applications,
0.026
0.66
Figure 22. Basic
2.032
0.08
0.711
0.028
but
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
power
semiconductor
0.635
0.025
SOLDERING FOOTPRINT*
BASIC PAD PATTERNS
http://onsemi.com
NTHC5513
8
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
0.457
0.018
0.635
0.025
0.026
0.66
Figure 23. Style 2
2.032
0.08
0.254
0.010
1.092
0.043
0.178
0.007

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