MX7575JN Maxim Integrated Products, MX7575JN Datasheet - Page 6

• Manufacturer Part Number: MX7575JN
• Description: Audio A/D Converter ICs
• Manufacturer: Maxim Integrated Products

Specifications of MX7575JN

• Conversion Rate: 200 KSPs
• Resolution: 8 bit
• Number Of Adc Inputs: 1
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

including the 8085A-2, test the status of the READY
input immediately after the start of an instruction cycle.
Therefore, if the MX7575/MX7576 are to be effective in
placing the µP in a wait state, their BUSY output should
go low very early in the cycle. When using the 8085A-2,
the earliest possible indication of an upcoming read
operation is provided by the S0 status signal. Thus, S0,
which is low for a read cycle, should be connected to
the RD input of the MX7575/MX7576. Figure 4 shows
the connection diagram for the 8085A-2 to the
MX7575/MX7576 in slow-memory interface mode.
Figure 5 shows the timing diagram for ROM interface
mode. In this mode, the µP does not need to be placed
in a wait state. A conversion is started with a read
instruction (RD and CS go low), and old data is
accessed. The BUSY signal then goes low to indicate
the start of a conversion. As before, the MX7575
track/hold acquires the signal on the third falling clock
edge after RD goes low, while the MX7576 samples it
eight times during a conversion. At the end of a conver-
sion (BUSY going high), another read instruction always
accesses the new data and normally starts a second
conversion. However, if RD and CS go low within one
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
Figure 3. Slow-Memory Interface Timing Diagram
Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface
6
BUSY
DATA
_______________________________________________________________________________________
* SOME CIRCUITRY OMITTED FOR CLARITY
CS
RD
S0 IS LOW FOR READ CYCLES
8085A-2
AD0–AD7
A8–A15
READY
IMPEDANCE
ALE
S0
HIGH-
BUS
t
1
t
3
t
2
ADDRESS
LATCH
ADDRESS BUS
OLD DATA
DATA BUS
ADDRESS
DECODE
t
CONV
t
6
+5V
ROM Interface Mode
TP/MODE
CS
RD
BUSY
D0–D7
DATA
NEW
MX7576
MX7575*
t
7
t
IMPEDANCE
5
HIGH-
BUS
external clock period of BUSY going high, then the sec-
ond conversion is not started. Furthermore, for correct
operation in this mode, RD and CS should not go low
before BUSY returns high.
Figures 6 and 7 show the connection diagrams for
interfacing the MX7575/MX7576 in the ROM interface
mode. Figure 6 shows the connection diagram for the
6502/6809 µPs, and Figure 7 shows the connections for
the Z-80.
Due to their fast interface timing, the MX7575/MX7576
will interface to the TMS32010 running at up to 18MHz.
Figure 8 shows the connection diagram for the
TMS32010. In this example, the MX7575/MX7576 are
mapped as a port address. A conversion is initiated by
using an IN A and a PA instruction, and the conversion
result is placed in the TMS32010 accumulator.
Tying the MODE pin low places the MX7576 into a con-
tinuous conversion mode. The RD and CS inputs are
only used for reading data from the converter. Figure 9
shows the timing diagram for this mode of operation,
and Figure 10 shows the connection diagram for the
8085A. In this mode, the MX7576 looks like a ROM to
Figure 5. ROM Interface Timing Diagram
Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface
DATA
BUSY
CS
RD
* SOME CIRCUITRY OMITTED FOR CLARITY
6502-6809
IMPEDANCE
HIGH-
BUS
t
A0–A15
1
2 OR E
D0–D7
t
t
2
Asynchronous Conversion Mode (MX7576)
3
R/W
DATA
t
OLD
4
EN
HIGH-IMPEDANCE BUS
t
5
t
ADDRESS BUS
7
DATA BUS
ADDRESS
DECODE
t
8
+5V
t
3
TP/MODE
CS
RD
D0–D7
DATA
NEW
MX7576
MX7575*
t
7
IMPEDANCE
HIGH-
BUS