CS5342-CZZR Cirrus Logic Inc, CS5342-CZZR Datasheet - Page 15

• Manufacturer Part Number: CS5342-CZZR
• Description: Audio A/D Converter ICs IC 105dB 192 kHz Multi-bit Audio ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5342-CZZR

• Conversion Rate: 192 KSPs
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.14 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS608F1
4.2.1
4.2.2
MCLK
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in
Operation as a Clock Slave
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-
Speed Mode. In Double-Speed and Quad-Speed Modes, the serial clock must be derived synchronously
from the master clock and equal to 48x Fs. Additionally, Quad-Speed Slave Mode is only specified for
operation with a VA and VD at 5 V, ±5%.
A unique feature of the CS5342 is the automatic selection of either Single-, Double- or Quad-Speed Mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (768x, 384x, and 192x for Single-, Double-, and Quad-
Speed Modes respectively). Please refer to
Figure
÷ 1.5
18.
÷ 3
Figure 18. CS5342 Master Mode Clocking
Auto-Select
0
1
Table 1 on page 14
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
for supported sample rate ranges.
Double
Speed
Speed
Speed
Single
Speed
Speed
Speed
Single
Quad
Quad
M[1:0]
00
01
10
00
01
10
SCLK Output
LRCK Output
(Equal to Fs)
CS5342
15