WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 123

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

w
Production Data
CLASS D SWITCHING CLOCK
The Class D switching clock is derived from SYSCLK as determined by register field DCLKDIV as
described in Table 70. This clock should be set to between 700kHz and 800kHz for optimum
performance. The class D switching clock should not be disabled when the speaker output is active,
as this will prevent the speaker outputs from functioning. The class D switching clock frequency
should not be altered while the speaker output is active as this may generate an audible click.
Table 70 DCLK Control
TOCLK CONTROL
A slow clock (TOCLK) is derived from SYSCLK to enable input de-bouncing and volume update
timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled
by TOCLK_RATE, as described in Table 71.
Table 71 TOCLK Control
USB MODE
It is possible to reduce power consumption by disabling the PLL in some applications. One such
application is when SYSCLK is generated from a 12MHz USB clock source. Setting the
AIF_LRCLKRATE bit as described earlier (see “ADC / DAC Sample Rates”) allows a sample rate
close to 44.1kHz to be generated with no additional PLL power consumption.
In this configuration, SYSCLK must be driven directly from MCLK (or MCLK2) and by disabling the
PLL. This is achieved by setting SYSCLK_SRC=0, PLL_ENA=0.
Table 72 USB Mode Control
R6 (06h)
R6 (06h)
R10 (0Ah)
REGISTER
REGISTER
ADDRESS
ADDRESS
REGISTER
ADDRESS
8:6
15
14
BIT
BIT
10
BIT
DCLKDIV
[2:0]
TOCLK_RATE
TOCLK_ENA
AIF_LRCLKRATE
LABEL
LABEL
LABEL
DEFAULT
DEFAULT
111b
0b
0b
DEFAULT
0b
Class D Clock Divider
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
Timeout Clock Rate
(Selects clock to be used for volume
update timeout and GPIO input de-
bounce)
0 = SYSCLK / 2
1 = SYSCLK / 2
Timeout Clock Enable
(This clock is required for volume update
timeout and GPIO input de-bounce)
0 = disabled
1 = enabled
0 = Normal mode (256 * fs)
1 = USB mode (272 * fs)
LRCLK Rate
DESCRIPTION
DESCRIPTION
DESCRIPTION
21
19
PD, March 2009, Rev 4.0
(Slower Response)
(Faster Response)
WM8990
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