CS8427-CSZR Cirrus Logic Inc, CS8427-CSZR Datasheet - Page 13
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CS8427-CSZR
Manufacturer Part Number
CS8427-CSZR
Description
Audio DSPs IC 96 kHz Digital Audio Transceiver
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8427-DZZ.pdf
(60 pages)
Specifications of CS8427-CSZR
Operating Temperature Range
- 10 C to + 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-28
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Channel Status bits. The part also has a feature
that allows the first five bytes of Channel Status
memory to be configured and transmitted in each
channel status block without change. See
dix A: External AES3/SPDIF/IEC60958 Transmit-
ter and Receiver Components” on page 50
tutorial in Channel Status and User bit manage-
ment.
3.4
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advis-
able to have current copies of the AES3 and
IEC60958 specifications on hand for easy refer-
ence.
The latest AES3 standard is available from the Au-
dio Engineering Society or ANSI at
www.ansi.org. Obtain the latest IEC60958 stan-
dard from ANSI or from the International Electro-
technical Commission at www.iec.ch. The latest
DS477F5
AES3 and S/PDIF Standards
Documents
SDA/CDOUT
AD2/EMPH
SCL/CCLK
AD1/CDIN
AD0/CS
ILRCK
ISCLK
SDIN
RXN
RXP
INT
Receiver
Serial
Audio
Input
User Data
AES3
Recovery
Channel
Status
and
Figure 6. CS8427 Internal Block Diagram
www.aes.org
Status Bits
User Bits
Channel
“Appen-
Control
Port
D
D
for a
or
EIAJ CP-1201 standard is available from the Jap-
anese Electronics Bureau.
Crystal Application Note AN22: Overview of Digital
Audio Interface Data Structures contains a useful
tutorial on digital audio specifications, but it should
not be considered a substitute for the standards.
The paper, An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
4. DATA I/O FLOW AND CLOCKING
The CS8427 can be configured for several connec-
tivity alternatives, called data flows.
ware Mode Audio Data Flow Switching Options” on
page 19
the control register bits which control the switches;
this drawing only shows the audio data paths for
simplicity. This drawing only shows the audio data
paths for simplicity.
TXD1-0
SPD1-0
Registers
Control
OPTIONS
E
E
Encoder
AES3
shows the data flow switching, along with
Generator
AESBP
Output
Clock
F
F
Serial
Audio
Output
Figure 8
TXOFF
shows the internal
OLRCK
OSCLK
SDOUT
TXP
TXN
OMCK
Figure 7. “Soft-
CS8427
13