WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 76

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
DIGITAL AUDIO INTERFACE
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The digital audio interface is used for inputting DAC data into the WM8903 and outputting ADC data
from it. It uses four pins:
•
•
•
•
Note that the BCLK pin can also support other functions, as described under “General Purpose
Input/Output (GPIO)”. BCLK is the default function on this pin (GP5_FN = 1h). Under default
conditions, the other GPIO control fields for this pin have no effect.
MASTER AND SLAVE MODE OPERATION
The LRC and BCLK pins can be independently configured as either inputs or outputs, as shown in
Table 51.
Table 51 Audio Interface Pin Direction Control
When both LRC and BCLK are configured as outputs, the WM8903 operates as a master device and
controls the timing of data transfer on the ADCDAT and DACDAT pins (see Figure 36). When both
LRC and BCLK are configured as inputs, the WM8903 operates as a slave device, and data timing is
controlled by an external master (see Figure 37). Additionally, two “mixed” modes (BCLK as input,
LRC as output and vice versa) can be selected.
When BCLK is not selected (GP5_FN ≠ 1), the WM8903 uses the MCLK input as the Bit Clock,
provided that BCLK_DIR is set to 0 to configure BCLK as an input, ie. BCLK slave mode. This
configuration can offer power consumption benefits in addition to flexibility of GPIO functionality,
Figure 36 Master Mode
When the BCLK pin is an output (BCLK_DIR=1), BCLK is derived from the internal CLK_SYS signal
(see “Clocking and Sample Rates”). In this case, the BCLK frequency is controlled in relation to
CLK_SYS by the BCLK_DIV register field. When BCLK is an input, BCLK_DIV has no effect.
When the LRC pin is an output (LRCLK_DIR=1), LRC is derived from BCLK (irrespective of whether
BCLK is an input or output). In this case, the LRC frequency is controlled in relation to BCLK by the
LRCLK_RATE register field. When LRC is an input, LRCLK_RATE has no effect.
R25 (19h)
Audio
Interface 1
REGISTER
ADDRESS
ADCDAT: ADC data output
DACDAT: DAC data input
LRC: DAC and ADC data alignment clock
BCLK: Bit clock, for synchronisation
BIT
9
6
LRCLK_DIR
BCLK_DIR
LABEL
DEFAULT
0
0
Figure 37 Slave Mode
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
PP, Rev 3.1, August 2009
DESCRIPTION
Pre-Production
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