WM8350GEB/RV Wolfson Microelectronics, WM8350GEB/RV Datasheet - Page 48

• Manufacturer Part Number: WM8350GEB/RV
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8350GEB/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8350
Figure 35 Audio CODEC Clocking
w
MCLK
ADCLRCLK
DACLRCLK
Crystal Oscillator /
GPIO 32kHz input
SYSCLK
All internal clocks are derived from SYSCLK, either directly
from MCLK or via the Frequency Locked Loop (FLL). The FLL
takes MCLK, ADCLRCLK, DACLRCLK or 32kHz input as its
reference.
ADC_CLKDIV
ADC sample rate is set by ADC_CLKDIV (Master or slave
mode).
DAC_CLKDIV
DAC sample rate is set by DAC_CLKDIV (Master or slave
mode).
BCLKDIV
BCLK rate is set by BCLKDIV in Master mode.
When ADC and DAC operate at different sample rates (in
master or slave mode), BCLK rate should be high enough to
support the higher of the ADC/DAC sample rates.
ADCLRCLK, ADCBCLK
These signals can be provided for the ADC via GPIO pins.
When these are used, the LRCLK and BCLK pins are used by
the DAC only.
OPCLK_DIV
GPIO Clock output frequency is set by OPCLK_DIV.
TOCLKSEL
A slow clock is used for jack detect debounce and for volume
update timeouts (when zero-crossing is enabled). The
frequency of this slow clock is set by TOCLK_RATE.
Other Sample Rate Controls
DEEMP configures the de-emphasis filter for the chosen
sample rate.
FLL_CLK_SRC
R45[1:0]
f
When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output
on this pin to provide clocking for other parts of the system. The frequency of this signal is set by
OPCLK_DIV.
Alternate GPIO pins can be used to provide ADCLRCLK and ADCBCLK as described in Section 20.
An inverted L/R clock signal ADCLRCLKB can also be generated. When this feature is used, the
LRCLK and BCLK pins support the DAC only, and the alternate GPIO pins support the ADC only.
Limited capability can be provided to support mixed sample rates by this method. (The selection of
USB mode and the supported values of the various SYSCLK dividers impose restrictions on what
combinations of clocking and sample rates may be configured.)
A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect
function, and to set the timeout period for volume updates when zero-cross functions are used. This
clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The overall CODEC clocking scheme is illustrated in Figure 35.
REF
FLL
f
OUT
MCLK_SEL
R40[11]
f/N
MCLK_DIV
R40[8]
1, 2
SYSCLK
TOCLK_ENA
R40[15]
BCLKDIV[3:0]
R40[7:4]
1, 1.5, 2, 3, 4, 5.5, 6, 8,
11, 12, 16, 22, 24, 32
ADCLRC_RATE[10:0]
R70[10:0]
1 .. 2047
f/N
DAC_CLKDIV[2:0]
R54[2:0]
1, 1.5, 2, 3, 4, 5.5, 6
ADC_CLKDIV[2:0]
R68[2:0]
1, 1.5, 2, 3, 4, 5.5, 6
OPCLK_DIV[2:0]
R40[2:0]
1, 2, 3, 4, 5.5, 6
f/N
f/N
f/N
SLOWCLK
DACLRC_RATE[10:0]
R53[10:0]
1 .. 2047
ADC_SYSCLK
DAC_SYSCLK
f/N
f/N
f/2
f/2
TOCLK_RATE
21
19
R40[14]
DACLRC_ENA
BCLK_MSTR
ADCLRC_ENA
R115[14]
R53[11]
R70[11]
f/4
f/4
GP6_FN[3:0]
GP8_FN[3:0]
Jack detect debounce,
Volume update timeout
R141[11:8]
R112[13]
AIF_TRI
R142[3:0]
ADC
DAC
GP5_FN[3:0]
LRC_ADC_SEL
R141[7:4]
PD, February 2011, Rev 4.4
64fs
64fs
R41[15]
ADCBCLK
(GPIO8)
ADCLRCLK / CODEC_OPCLK
(GPIO5)
ADCLRCLKB
(GPIO6)
LRCLK
(master mode output)
BCLK
(master mode output)
Production Data
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