CS4222-KS Cirrus Logic Inc, CS4222-KS Datasheet - Page 22

• Manufacturer Part Number: CS4222-KS
• Description: Audio CODECs IC 20-Bit Stereo Codec w/Vol Cntrl
• Manufacturer: Cirrus Logic Inc

Specifications of CS4222-KS

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4.7 De-Emphasis
The CS4222 is capable of digital de-emphasis for 32, 44.1, or 48 kHz sample rates. Implementation of digital
de-emphasis requires reconfiguration of the digital filter to maintain the filter response at multiple sample rates
(see Figure 13).
De-emphasis control is achieved with the DEM1/0 pins or through the DEM2-0 bits in the DSP Port Mode Byte
(#2). The default state on power-up is de-emphasis controlled via the DEM1/0 pins (DEM2-0 bits=0). DEM1/0
pin control is defined in Table 4.
4.6.2 I
In I
the clock-to-data relationship as shown in Figure 12. There is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VD or DGND as desired. The upper 6 bits of the 7 bit address field must be
001000. In order to communicate with the CS4222, the LSB of the chip address field (first byte sent to the
CS4222) should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for
a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects
the register to be read or written. If the operation is a read, the contents of the register pointed to by the
Memory Address Pointer will be output. Setting the auto increment bit in MAP allows successive reads or
writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.6.3 Control Port Bit Definitions
All registers can be written and read in I
CLKE and CALP bits in the ADC control byte (#1) which are read only. SPI mode only allows for register
writing (see the following bit definition tables for bit assignment information).
DEM 1
Table 4. De-Emphasis filter control
2
0
0
1
1
C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with
SDA
SCL
2
C Mode
Start
001000
DEM 0
0
1
0
1
Figure 12. Control Port Timing, I
ADDR
AD0
De-emphasis
44.1 kHz
32 kHz
48 kHz
OFF
R/W
2
C mode, except the Converter Status Report Byte (#6) and the
ACK
DATA 1-8
-10 dB
Gain
dB
0 dB
Figure 13. De-emphasis Curve.
ACK
2
C mode
T1 = 50 µs
DATA 1-8
F1
ACK
Stop
F2
T2 = 15 µs
Frequency
CS4222
DS236F1