W134SH Silicon Laboratories Inc, W134SH Datasheet

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Features • Differential clock source for Direct Rambus™ memory subsystem for up to 800-MHz data transfer rate • Provide synchronization flexibility: the Rambus Channel can optionally be synchronous to an external system or processor clock • Power-managed output allows Rambus ...

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Pin Definitions Pin Name No. Type REFCLK 2 I Reference Clock Input. Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). PCLKM 6 I Phase Detector Input. The phase difference between this signal and SYNCLKN is used ...

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Key Specifications Supply Voltage:...................................... V Operating Temperature: ................................... 0°C to +70°C Input Threshold:...................................................1.5V typical Maximum Input Voltage: ........................................ V Maximum Input Frequency: ..................................... 100 MHz Output Duty Cycle:................................... 40/60% worst case Output Type: ........................... Rambus signaling level (RSL) DDLL System ...

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W133 W158 W159 W161 W167 CY2210 RMC Pclk Figure 3 shows more details of the DDLL system architecture, including the DRCG output enable and bypass modes. Phase Detector Signals The DRCG Phase Detector receives two inputs from the core logic, ...

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Table 4. Bypass and Test Mode Selection Bypclk Mode S0 S1 (int.) Normal 0 0 Gnd Output Test (OE – Bypass 1 0 PLLclk Test 1 1 Refclk Table 5 shows the logic for selecting the Power-down mode, ...

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Timing Diagrams Power-down Exit and Entry PwrDnB Clk/ClkB Output Enable Control StopB Clk/ClkB Mult0 and/or Mult1 Clk/ClkB Table 8. State Transition Latency Specifications Transition From A Power-down C Power-down Clk Stop K Power-down ...

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Table 8. State Transition Latency Specifications (continued) Transition From E Clk Stop E Clk Stop F Normal Clk Stop L Test N Normal B,D Normal or Clk Stop Power-down t Figure 5 shows that the Clk Stop to Normal transition ...

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Absolute Maximum Conditions Parameter V Max. voltage on V DD, ABS V Max. voltage on any pin with respect ground I, ABS [2] External Component Values Parameter R Serial Resistor S R Parallel Resistor P C Edge Rate Filter Capacitor ...

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Device Characteristics Parameter t Clock Cycle Time CYCLE t Cycle-to-Cycle Jitter at Clk/ClkB J Total Jitter over Clock Cycles 266-MHz Cycle-to-Cycle Jitter 266-MHz Total Jitter over Clock Cycles t Phase Aligner Phase ...

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... Layout Example VDDIR VDDIPD Ordering Information Ordering Code W134H W134HT W134SH W134SHT Lead-free CYW134MOXC CYW134MOXCT CYW134SOXC CYW134SOXCT Rev 1.0, November 24, 2006 +3.3V Supply FB 0.005 μF 10 μ Internal Power Supply Plane FB = Dale ILB1206 - 300 (300Ω @ 100 MHz VIA to GND plane layer All Bypass cap = 0 ...

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Package Diagram While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which ...