SL23EP05SI-1 Silicon Laboratories Inc, SL23EP05SI-1 Datasheet - Page 3

• Manufacturer Part Number: SL23EP05SI-1
• Description: Clock Buffer 10-220MHz 5 Outputs ZDB 3.3-2.5V
• Manufacturer: Silicon Laboratories Inc

Specifications of SL23EP05SI-1

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 2.2, June 30, 2009
General Description
The SL23EP05 is a low skew, low jitter Zero Delay Buffer with
very low operating current.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces five (5)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
In addition to CLKOUT that is used for internal PLL feedback,
there is a single bank with four (4) outputs, bringing the
number of total available output clocks to five (5).
Input and output Frequency Range
The input and output frequency range is the same. But, it
depends on VDD and drive levels as given in the below
Table 1.
If the input clock frequency is DC (0 to VDD), this is detected
by an input frequency detection circuitry and all five (5) clock
outputs are forced to Hi-Z. The PLL is shutdown to save
power. In this shutdown state, the product draws less than
10μA supply current.
SpreadThru
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP05 is designed to pass the modulated
Spread Spectrum Clock (SSC) signal from its reference input
to the output clocks. The same spread characteristics at the
input are passed through the PLL and drivers without any
degradation in spread percent (%), spread profile and
modulation frequency.
VDD(V)
3.3
3.3
2.5
2.5
Table 1. Input/Output Frequency Range
™
Drive
Feature
HIGH
HIGH
STD
STD
Min(MHz) Max(MHz)
10
10
10
10
220
200
180
167
High and Low-Drive Product Options
The SL23EP05 is offered with High-Drive “-1H” and Standard-
Drive “-1” options. These drive options enable the users to
control load levels, frequency range and EMI control. Refer to
the AC electrical tables for the details.
Skew and Zero Delay
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the AC
electrical tables. However, Zero delay between input and
outputs can be adjusted by changing the loading of CLKOUT
relative to the banks A and B clocks since CLKOUT is the
feedback to the PLL.
Power Supply Range (VDD)
The SL23EP05 is designed to operate in a wide power supply
range from 2.250V (Min) to 3.360V (Max). This power supply
range complies with 3.3V+/-10% and 2.5V+/-10% standard
power supply requirements used in most systems. An internal
on-chip voltage regulator is used to supply PLL constant
power supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, and jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL05.
SL23EP05
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