CY28409OC Silicon Laboratories Inc, CY28409OC Datasheet - Page 9

• Manufacturer Part Number: CY28409OC
• Description: Clock Synthesizer / Jitter Cleaner SysClk Intel Grntsdl 865 and 875 chipsets
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28409OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 22, 2006
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPUC, 133MHz
CPUT, 133MHz
CPU_STP#
SRCC 100MHz
SRCT 100MHz
CPU Internal
3V66, 66MHz
CPU_STP#
USB, 48MHz
PCI, 33MHz
CPUT
CPUC
CPUT
CPUC
PD#
REF
Figure 4. Power-down Deassertion Timing Waveform
Figure 6. CPU_STP# Deassertion Waveform
Figure 5. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#, 10 ns > 200 mV
<300 μs, >200 mV
Tdrive_PWRDN#
<1.8 ms
Tstable
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CY28409
Page 9 of 16