CY28400OC Silicon Laboratories Inc, CY28400OC Datasheet - Page 8

• Manufacturer Part Number: CY28400OC
• Description: Clock Buffer 100 MHz Diff Buffer PCI Express & SATA
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28400OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Output Enable Clarification
The outputs may be disabled in two ways, via writing a ‘0’ to
the SMBus register bit corresponding to output of interest or
by asserting an OE input pin LOW. In both methods, if SMBus
registered bit has been written LOW or the OE pin is LOW or
both, the output of interest will be three-stated. The assertion
and deassertion of this signal is asynchronous.
Table 6. OE Functionality
OE Assertion
All differential outputs that were three-stated will resume
normal operation in a glitch-free manner. The maximum
latency from the assertion to active outputs is between 2–6 DIF
clock periods. In addition, DIFT clocks will be driven HIGH
within 10 ns of OE assertion to a voltage greater than 200 mV.
OE Deassertion
The impact of deasserting OE is that each corresponding output
will transition from normal operation to three-state in a
glitch-free manner. The maximum latency from the deassertion
to three-stated outputs is between 2–6 DIF clock periods.
SRC_DIV2# Clarification
The SRC_DIV2# feature is used to configure the DIF output
mode to be equal to the SRCT_IN input frequency or half the
input frequency in a glitch-free manner. The SRC_DIV2# function
may be implemented by writing a ‘0’ to SMBus register bit.
OE (Pin)
1
1
0
0
DIFC(Free Running
DIFT(Free Running
DIFC(Free Running
DIFT(Free Running
DIFC (Stoppable)
DIFT (Stoppable)
OE (SMBus Bit)
DIFC (Stoppable)
DIFT (Stoppable)
SRC_STOP#
SRC_STOP#
PWRDWN#
PWRDWN#
(Transition from ‘0’ to ‘1’)
1
0
1
0
(Transition from ‘1’ to ‘0’)
Figure 7. SRC_STOP# = Three-state, PWRDWN# = Three-state
Figure 6. SRC_STOP# = Three-state, PWRDWN# = Driven
Three-state
Three-state
Three-state
Normal
DIFT
Three-state
Three-state
Three-state
Normal
DIFC
SRC_DIV2# Assertion
The impact of writing a ‘0’ to the SRC_DIV/2 register bit is that
all DIF outputs will transition cleanly in a glitch-free manner
from normal operation (output frequency equal to input) to half
the input frequency within 2–6 DIF clock periods.
SRC_DIV2# Deassertion
The impact of writing a ‘0’ to the SRC_DIV/2 register bit is that
all DIF outputs will transition cleanly in a glitch-free manner
from divide by 2 mode to normal (output frequency is equal to
the input frequency) operation within 2–6 DIF clock periods.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass
mode (no PLL) and PLL mode. In bypass mode, the input clock
is passed directly to the output stage resulting in 50 ps additive
jitter (50 ps + input jitter) on DIF outputs. In the case of PLL
mode, the input clock is pass through a PLL to reduce
high-frequency jitter. The BYPASS# mode may be selected in
two ways, via writing a ‘0’ to SMBus register bit or by asserting
the PLL/BYPASS# pin LOW. In both methods, if the SMBus
register bit has been written low or PLL/BYPASS# pin is LOW
or both, the device will be configure for BYPASS operation.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This
mode is intended to minimize PLL peaking when two or more
buffers are cascaded by staggering device bandwidths. The
PLL low-bandwidth mode may be selected in two ways, via
writing a ‘0’ to SMBus register bit or by asserting the
HIGH_BW# pin is LOW or both, the device will be configured
for low-bandwidth operation.
1mS
1mS
CY28400
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