CY28RS480ZXC Silicon Laboratories Inc, CY28RS480ZXC Datasheet - Page 5

• Manufacturer Part Number: CY28RS480ZXC
• Description: Clock Generators & Support Products ATIR RS480 Chipset System Clock
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28RS480ZXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 22, 2006
Byte 2: Control Register 2
Byte 3: Control Register 3
Byte 4: Control Register 4
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
0
0
0
1
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
CLKREQ#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPUT/C
SRCT/C
USB_48
HTT66
HTT66
Name
Name
Name
CPU
SRC
CPU
SRC
PCI
Reserved
Reserved
Reserved
Reserved
Spread Spectrum Selection
‘0’ = –0.35%
‘1’ = –0.50%
48-MHz Output Drive Strength
0 = 2x, 1 = 1x
33-MHz Output Drive Strength
0 = 2x, 1 = 1x
Reserved
Reserved
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Reserved
Reserved
CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
CPU pd drive mode
0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state
SRC pd drive mode
0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state
HTT66 Output Drive Strength0 = High drive, 1 = Low drive.
SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
HTT66 Output enable
0 = Disabled, 1 = Enabled
Description
Description
Description
CY28RS480
Page 5 of 14