CY2SSTV855ZXC Silicon Laboratories Inc, CY2SSTV855ZXC Datasheet - Page 5

• Manufacturer Part Number: CY2SSTV855ZXC
• Description: Clock Buffer 2.5V 170MHz 1:5 Differential DDR PLL
• Manufacturer: Silicon Laboratories Inc

Specifications of CY2SSTV855ZXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.1, September 25, 2007
Absolute Maximum Conditions
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum Power Supply: ................................................ 3.5V
DC Electrical Specifications (
AC Electrical Specifications (
V
V
I
I
I
V
V
V
V
I
I
I
Cin
f
t
t
t
t
t
t
t
Notes:
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a
12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
13. Refers to transition of non-inverting output.
14. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 6.
Parameter
IN
OL
OH
OZ
DDQ
DD
Parameter
CLK
DC
LOCK
SL(O)
PZL
PLZ
CCJ
JITT(H-PER)
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
6. Differential cross-point input voltage is expected to track V
7. For load conditions see Figure 6.
8. The value of V
9. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 6.
ID
IX
OL
OH
OUT
OC
mentary input level.
downspread of –0.5%
where the cycle time (t
, t
, t
PZH
PHZ
Differential Input Voltage
Differential Input Crossing Voltage
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
Output Crossing Voltage
High-Impedance Output Current
Dynamic Supply Current
PLL Supply Current
Input Pin Capacitance
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Cycle to Cycle Jitter
Half-period jitter
OC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6.
C
) decreases as the frequency goes up.
Description
Description
SS
DDQ
:............................... V
or AV
[7]
[5]
[8]
DD
[12]
AV
[9]
AV
: ............. V
[3]
DD
DD
= V
= V
[13]
[13]
DDQ
[6]
DDQ
DDQ
DD
SS
CLKINT, FBINT
CLKTIN, FBINT
V
FBINT
V
V
V
V
V
V
AV
AV
20% to 80% of VOD
f > 66 MHz
f > 66 MHz
and is the voltage at which the differential signals must be crossing.
= 2.5V ± 5%, T
= 2.5V±5%, T
IN
DDQ
DDQ
DDQ
DDQ
O
DDQ
– 0.3V
+ 0.3V
DD
= GND or V
= 0V or V
DD
= 2.375V, V
= 2.375V, V
= 2.375V, I
= 2.375V, I
only
= 170 MHz
= 2.5V ± 0.2V
Conditions
Conditions
IN
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
A
= V
O
SS
A
= –40° C to +85° C)
OL
OH
= V
OUT
OUT
= –40° C to +85° C)
DDQ
< (V
= 12 mA
= –12 mA
DDQ
= 1.2V
= 1V
, CLKINT,
in
or V
out
) < V
(V
(V
[10, 11]
DDQ
SS
–100
–100
DDQ
DD
[4]
Min.
Min.
0.36
in
–10
–18
–10
0.2
1.7
1.1
60
40
0.2
26
1
–
–
–
and V
.
or V
/2) –
/2) –
DD
out
).
V
V
should be constrained to the
Typ.
DDQ
DDQ
Typ.
–32
235
35
30
10
CY2SSTV855
–
–
–
–
9
4
/2 (V
/2 (V
V
V
DDQ
DDQ
DDQ
DDQ
Max.
Max.
Page 5 of 8
170
100
100
100
300
0.2
0.6
0.2
60
10
10
12
2
–
–
–
–
+ 0.6
– 0.4
/2) +
/2) +
WH
MHz
V/ns
Unit
Unit
mA
mA
mA
mA
µA
µA
pF
µs
ns
ns
ps
ps
/t
%
V
V
V
V
V
V
C
,