CY28401OC Silicon Laboratories Inc, CY28401OC Datasheet - Page 4

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CY28401OC

Manufacturer Part Number
CY28401OC
Description
Clock Buffer 100 MHz Diff Buffer PCIe & SATA 1in 4out
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of CY28401OC

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.0, November 21, 2006
Byte 0: Control Register 0 (continued)
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
@pup
@pup
@pup
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Name
Name
Name
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
PLL/Bypass#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV/2
0 = Divided by 2 mode, 1 = Normal (output = input)
DIF_7 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_6 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_5 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_4 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_3 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_2 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_1 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_0 Output Enable
0 = Disabled (three-state)
1 = Enabled
Allow Control DIF_7 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_6 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_5 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_4 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Description
Description
Description
CY28401
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