CY28401OXC Silicon Laboratories Inc, CY28401OXC Datasheet - Page 2

• Manufacturer Part Number: CY28401OXC
• Description: Clock Buffer 100 MHz Diff Buffer PCIe & SATA 1in 4out
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28401OXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Pin Description
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
4,5
8,9,12,13,16,17,20,21,29,30,
33,34,37,38,41,42
6,7,14,15,35,36,43,44
28
45
26
1
27
23
24
46
22
48
47
3,10,18,25,32,40
2,11,19,31,39
(6:0)
2:8
Bit
Bit
7
1
9
Pin
Slave address – 7 bits
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Start
Write = 0
Block Write Protocol
SRCT_IN, SRCC_IN
DIFT/C(7:0)
OE_(7:0)
HIGH_BW#
LOCK
PWRDWN#
SRC_DIV/2#
SRC_STOP#
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
Description
Name
I/O,OC Open collector SMBus data
O,DIF 0.7V Differential Clock Outputs
O,SE
Type
GND
I,DIF
3.3V
I,SE
I,SE
I,SE
I,SE
I,SE
I,SE
I
I
I
I
0.7V Differential SRC inputs from the clock synthesizer
3.3V LVTTL active LOW input for three-stating differential
outputs
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
3.3V LVTTL input for Power-down, active LOW
3.3V LVTTL input for selecting input frequency divided by
two, active LOW
3.3V LVTTL input for SRC_Stop#, active LOW
SMBus Slave Clock Input
A precision resistor is attached to this pin to set the differ-
ential output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V Power Supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
Description
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
2:8
Bit
1
9
Start
Slave address – 7 bits
Write = 0
Block Read Protocol
Description
Description
CY28401
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