MCP7940NT-I/MS Microchip Technology, MCP7940NT-I/MS Datasheet - Page 15

• Manufacturer Part Number: MCP7940NT-I/MS
• Description: Real Time Clock I2C GP RTCC 64B SRAM
• Manufacturer: Microchip Technology
• Series: -r
• Type: Clock/Calendarr

Specifications of MCP7940NT-I/MS

• Features: Alarm, Leap Year, SRAM
• Memory Size: 64B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 5.5 V
• Voltage - Supply, Battery: 1.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
5.2.1
Following the Start condition from the master, the
control code and the R/W bit (which is a logic low) are
clocked onto the bus by the master transmitter. This
indicates to the addressed slave receiver that a byte
with a word address will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
FIGURE 5-3:
5.2.2
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
5.2.2.1
The MCP7940N contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the MCP7940N issues an Acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition and the
MCP7940N discontinues transmission
FIGURE 5-4:
 2011 Microchip Technology Inc.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
RTCC/SRAM
Current Address Read
SRAM BYTE WRITE
READ OPERATION
S
S
T
A
R
T
1
1
CONTROL
0
BYTE
1
SRAM BYTE WRITE
CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
1 1 1
1
A
C
K
x = don’t care for 1K devices
(Figure
BYTE
DATA
S 1 1 0 1
S
T
A
R
T
CONTROL
5-4).
BYTE
N
O
A
C
K
1 1 1
S
T
O
P
P
0
A
C
K
x
ADDRESS
Pointer of the MCP7940N. After receiving another
Acknowledge signal from the MCP7940N, the master
device transmits the data word to be written into the
addressed
acknowledges again and the master generates a Stop
condition. After a Byte Write command, the internal
address counter will point to the address location
following the one that was just written.
5.2.2.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
MCP7940N as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The MCP7940N will then issue an Acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but it does generate a Stop
condition which causes the MCP7940N to discontinue
transmission
command, the internal address counter will point to the
address location following the one that was just read.
BYTE
Note:
Addressing undefined SRAM locations will
result
acknowledging the address.
Random Read
A
C
K
memory
(Figure
DATA
in
5-5). After a Random Read
location.
MCP7940N
the
A
C
K
S
T
O
P
P
MCP7940N
The
DS25010A-page 15
MCP7940N
not