PI6C48545LEX Pericom Semiconductor, PI6C48545LEX Datasheet - Page 2

• Manufacturer Part Number: PI6C48545LEX
• Description: Clock Buffer 3.3V Low Skew 1:4 LVTTL/LVCMOS
• Manufacturer: Pericom Semiconductor

Specifications of PI6C48545LEX

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
Notes:
1.
Pin Characteristics
Control Input Function Table
Notes:
1.
GND
CLK_EN
CLK_SEL
CLK
CLK
NC
OE
V
Q
Q
Q
Q
CC
3
2
1
0
R_pulldown
,
,
,
,
Name
I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
R_pullup
n
n
n
n
Symbol
OE
0
1
Q
Q
Q
Q
1
1
1
1
0
C
3
2
1
0
IN
1, 9, 13
10, 18
11, 12
14, 15
16, 17
19, 20
Pin #
5, 7
CLK_EN
2
3
4
6
8
Input Pulldown Resistance
Input Pullup Resistance
0
0
1
1
x
Input Capacitance
Parameter
Type
I_PU
I_PD
I_PD
I_PD
I_PU
O
O
O
O
P
P
Inputs
CLK_SEL
Connect to Ground
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80kΩ
pull up.
Clock select input. When high, selects CLK
LVCMOS/LVTTL level with 80kΩ pull down.
LVCMOS / LVTTL clock input
LVCMOS / LVTTL clock input
No internal connection.
Output Enable. Controls outputs Q
Connect to 3.3V.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
0
1
0
1
x
Selected Source
Conditions
CLK
CLK
CLK
CLK
0
1
0
1
2
0
,
n
Q
LVTTL/LVCMOS to LVDS Fanout Buffer
Description
Min.
0
through Q
Diasbled: Low
Disabled: Low
1
Enabled
Enabled
input. When low, selects CLK
Q
HiZ
0
:Q
3
3
, nQ
Typ.
80
80
3.
6
Outputs
3.3V Low Skew 1-to-4
Max.
Diasbled: High
Disabled: High
n
Enabled
Enabled
Q
PS8770
HiZ
0
0
:
input.
PI6C48545
n
Q
3
Units
kΩ
pF
06/23/05