PI6C180BVEX Pericom Semiconductor, PI6C180BVEX Datasheet - Page 5

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PI6C180BVEX

Manufacturer Part Number
PI6C180BVEX
Description
Clock Buffer Precision 1 18 Clock Buffer
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI6C180BVEX

Number Of Outputs
18
Propagation Delay (max)
5.5 ns
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
SSOP-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Minimum and Maximum Expected
Capacitive Loads
Notes:
1.
2.
3.
SDRAM
Clock
Maximum rise/fall times are guaranteed at maximum specified
load.
Minimum rise/fall times are guaranteed at minimum specified
load.
Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
06-0109
Load
Min.
15
Load
Max.
20
Waveform
Interface
Clocking
Units
Input
pF
Waveform
(TTL)
3.3V
Output
2.4
1.5
0.4
SDRAM DIMM
Specfication
t plh
t SDRISE
Notes
1.5V
Figure 1. Clock Waveforms
tSDKH
Output
Buffer
1.5V
t SDFALL
tSDKP
5
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
4. Position clock signals away from signals that go to any cables
Test Load
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specified values.
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
or any external connectors.
tSDKL
Test
Point
1.5V
1.5V
t phl
Precision 1-18 Clock Buffer
PS8468B
PI6C180B
06/20/06

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